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1. 发明授权

US08513067B2 Fabrication method for surrounding gate silicon nanowire transistor with air as spacers 有权
标题翻译：围绕栅极硅纳米线晶体管的制造方法，其中空气为间隔物
公开(公告)号：US08513067B2
公开(公告)日：2013-08-20
申请号：US13266791
申请日：2011-07-15
申请人： Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
发明人： Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
IPC分类号： H01L21/84
CPC分类号： H01L29/66439 , B82Y10/00 , H01L29/775
摘要： The invention discloses a fabrication method for a surrounding gate silicon nanowire transistor with air as spacers. The method comprises: performing isolation, and depositing a material A which has a higher etch selectivity ratio with respect to Si; performing photolithography to define a Fin hard mask; etching the material A to form the Fin hard mask; performing source and drain implantation; performing photolithography to define a channel region and large source/drain regions; forming the Si Fin and the large source/drains; removing the hard mask of the material A; forming a nanowire; etching the SiO2 to form a floating nanowire; forming a gate oxide layer; depositing a polysilicon; performing polysilicon injection; performing annealing to activate dopants; etching the polysilicon; depositing SiN; performing photolithography to define a gate pattern; etching the SiN and the polysilicon to form the gate pattern; separating the gate and the source/drain with a space in between filled with air; depositing SiO2 to form air sidewalls; performing annealing to densify the SiO2 layer; using subsequent processes to complete the device fabrication. The invention is compatible with the CMOS process flow. The introduction of the air sidewalls can effectively reduce the parasitic capacitance of the device, and improve the transient response of the device, so that the method is applicable for a logic circuit with high performance.
摘要翻译：本发明公开了一种具有空气作为间隔物的周围栅极硅纳米线晶体管的制造方法。该方法包括：执行隔离和沉积相对于Si具有较高蚀刻选择比的材料A; 执行光刻以限定Fin硬掩模; 蚀刻材料A以形成Fin硬掩模; 进行源极和漏极植入; 执行光刻以限定沟道区和大的源极/漏极区; 形成Si Fin和大源/排水; 去除材料A的硬掩模; 形成纳米线; 蚀刻SiO 2以形成浮动的纳米线; 形成栅氧化层; 沉积多晶硅; 执行多晶硅注入; 执行退火以激活掺杂剂; 蚀刻多晶硅; 沉积SiN; 执行光刻以限定栅极图案; 蚀刻SiN和多晶硅以形成栅极图案; 分离门和源/排水管之间的空间填充空气之间; 沉积SiO 2以形成空气侧壁; 进行退火以使SiO 2层致密化; 使用后续过程来完成器件制造。本发明与CMOS工艺流程兼容。空气侧壁的引入可以有效降低器件的寄生电容，提高器件的瞬态响应，使其适用于具有高性能的逻辑电路。

2. 发明授权

US08563370B2 Method for fabricating surrounding-gate silicon nanowire transistor with air sidewalls 有权
标题翻译：用于制造具有空气侧壁的环形栅极硅纳米线晶体管的方法
公开(公告)号：US08563370B2
公开(公告)日：2013-10-22
申请号：US13384215
申请日：2011-07-04
申请人： Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
发明人： Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
IPC分类号： H01L21/338
CPC分类号： H01L29/78696 , H01L21/76289 , H01L29/0673 , H01L29/42392 , H01L29/66772
摘要： A method for fabricating a surrounding-gate silicon nanowire transistor with air sidewalls is provided. The method is compatible with the CMOS process; the introduced air sidewalls can reduce the parasitic capacitance effectively and increase the transient response characteristic of the device, thus being applicable to a high-performance logic circuit.
摘要翻译：提供了一种制造具有空气侧壁的环形栅极硅纳米线晶体管的方法。该方法与CMOS工艺兼容; 引入的空气侧壁可以有效地减小寄生电容并增加器件的瞬态响应特性，从而适用于高性能逻辑电路。

3. 发明申请

US20130017654A1 FABRICATION METHOD FOR SURROUNDING GATE SILICON NANOWIRE TRANSISTOR WITH AIR AS SPACERS 有权
标题翻译：具有空气作为间隔件的环形硅纳米晶体管的制造方法
公开(公告)号：US20130017654A1
公开(公告)日：2013-01-17
申请号：US13266791
申请日：2011-07-15
申请人： Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
发明人： Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
IPC分类号： H01L21/336 , B82Y99/00
CPC分类号： H01L29/66439 , B82Y10/00 , H01L29/775
摘要： The invention discloses a fabrication method for a surrounding gate silicon nanowire transistor with air as spacers. The method comprises: performing isolation, and depositing a material A which has a higher etch selectivity ratio with respect to Si; performing photolithography to define a Fin hard mask; etching the material A to form the Fin hard mask; performing source and drain implantation; performing photolithography to define a channel region and large source/drain regions; forming the Si Fin and the large source/drains; removing the hard mask of the material A; forming a nanowire; etching the SiO2 to form a floating nanowire; forming a gate oxide layer; depositing a polysilicon; performing polysilicon injection; performing annealing to activate dopants; etching the polysilicon; depositing SiN; performing photolithography to define a gate pattern; etching the SiN and the polysilicon to form the gate pattern; separating the gate and the source/drain with a space in between filled with air; depositing SiO2 to form air sidewalls; performing annealing to densify the SiO2 layer; using subsequent processes to complete the device fabrication. The invention is compatible with the CMOS process flow. The introduction of the air sidewalls can effectively reduce the parasitic capacitance of the device, and improve the transient response of the device, so that the method is applicable for a logic circuit with high performance.
摘要翻译：本发明公开了一种具有空气作为间隔物的周围栅极硅纳米线晶体管的制造方法。该方法包括：执行隔离和沉积相对于Si具有较高蚀刻选择比的材料A; 执行光刻以限定Fin硬掩模; 蚀刻材料A以形成Fin硬掩模; 进行源极和漏极植入; 执行光刻以限定沟道区和大的源极/漏极区; 形成Si Fin和大源/排水; 去除材料A的硬掩模; 形成纳米线; 蚀刻SiO 2以形成浮动的纳米线; 形成栅氧化层; 沉积多晶硅; 执行多晶硅注入; 执行退火以激活掺杂剂; 蚀刻多晶硅; 沉积SiN; 执行光刻以限定栅极图案; 蚀刻SiN和多晶硅以形成栅极图案; 分离门和源/排水管之间的空间填充空气之间; 沉积SiO 2以形成空气侧壁; 进行退火以使SiO 2层致密化; 使用后续过程来完成器件制造。本发明与CMOS工艺流程兼容。空气侧壁的引入可以有效降低器件的寄生电容，提高器件的瞬态响应，使其适用于具有高性能的逻辑电路。

4. 发明申请

US20120302014A1 METHOD FOR FABRICATING SURROUNDING-GATE SILICON NANOWIRE TRANSISTOR WITH AIR SIDEWALLS 有权
标题翻译：用于制造具有空气平台的环形硅纳米晶体管的方法
公开(公告)号：US20120302014A1
公开(公告)日：2012-11-29
申请号：US13384215
申请日：2011-07-04
申请人： Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
发明人： Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/78696 , H01L21/76289 , H01L29/0673 , H01L29/42392 , H01L29/66772
摘要： A method for fabricating a surrounding-gate silicon nanowire transistor with air sidewalls is provided. The method is compatible with the CMOS process; the introduced air sidewalls can reduce the parasitic capacitance effectively and increase the transient response characteristic of the device, thus being applicable to a high-performance logic circuit.
摘要翻译：提供了一种制造具有空气侧壁的环形栅极硅纳米线晶体管的方法。该方法与CMOS工艺兼容; 引入的空气侧壁可以有效地减小寄生电容并增加器件的瞬态响应特性，从而适用于高性能逻辑电路。

5. 发明授权

US08592276B2 Fabrication method of vertical silicon nanowire field effect transistor 有权
标题翻译：垂直硅纳米线场效应晶体管的制造方法
公开(公告)号：US08592276B2
公开(公告)日：2013-11-26
申请号：US13501711
申请日：2011-11-18
申请人： Ru Huang , Jiewen Fan , Yujie Ai , Shuai Sun , Runsheng Wang , Jibin Zou , Xin Huang
发明人： Ru Huang , Jiewen Fan , Yujie Ai , Shuai Sun , Runsheng Wang , Jibin Zou , Xin Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/0676 , B82Y10/00 , B82Y40/00 , H01L29/66439 , H01L29/775
摘要： The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.
摘要翻译：本发明公开了一种具有低寄生电阻的垂直硅纳米线场效应晶体管的制造方法，其涉及超大集成电路制造技术的领域。与传统的平面场效应晶体管相比，一方面，本发明制造的垂直硅纳米线场效应晶体管可以提供良好的抑制由于一维结构引起的栅极控制能力的短通道效应的能力，并减少泄漏电流和漏极引起的屏障降低（DIBL）。另一方面，晶体管的面积进一步减小，并且IC系统的集成度增加。

6. 发明申请

US20120302027A1 Method for Fabricating Silicon Nanowire Field Effect Transistor Based on Wet Etching 有权
标题翻译：基于湿蚀刻的硅纳米线场效应晶体管的制造方法
公开(公告)号：US20120302027A1
公开(公告)日：2012-11-29
申请号：US13511123
申请日：2011-11-18
申请人： Ru Huang , Jiewen Fan , Yujie Ai , Shuai Sun , Runsheng Wang , Jibin Zou , Xin Huang
发明人： Ru Huang , Jiewen Fan , Yujie Ai , Shuai Sun , Runsheng Wang , Jibin Zou , Xin Huang
IPC分类号： H01L21/336 , B82Y40/00
CPC分类号： H01L29/66772 , H01L29/42392 , H01L29/78696
摘要： Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching. The method includes defining an active region; depositing a silicon oxide film as a hard mask, forming a pattern of a source and a drain and a fine bar connecting the source and the drain; transferring the pattern on the hard mask to a silicon substrate by performing etching process for the silicon substrate; performing ion implanting; etching the silicon substrate by wet etching, so that the silicon fine bar connecting the source and the drain is suspended; reducing the silicon fine bar to a nano size to form a silicon nanowire; depositing a polysilicon film; forming a polysilicon gate line acrossing the silicon nanowire by electron beam lithography and forming a structure of nanowire-all-around; forming a silicon oxide sidewall at both sides of the polysilicon gate line, by depositing a silicon oxide film and subsequently etching the silicon oxide film; forming the source and the drain by using ion implantation and high temperature annealing, so that the silicon nanowire field effect transistor is finally fabricated. The method is compatible with a conventional integrated circuit fabrication technology. The fabrication process is simple and convenient, and has a short cycle.
摘要翻译：本文公开了一种基于湿蚀刻制造硅纳米线场效应晶体管的方法。该方法包括定义活动区域; 沉积氧化硅膜作为硬掩模，形成源极和漏极的图案以及连接源极和漏极的细棒; 通过对硅衬底进行蚀刻处理，将硬掩模上的图案转移到硅衬底; 进行离子注入; 通过湿蚀刻蚀刻硅衬底，使得连接源极和漏极的硅细棒悬空; 将硅细棒还原成纳米尺寸以形成硅纳米线; 沉积多晶硅膜; 通过电子束光刻形成跨越硅纳米线的多晶硅栅极线，并形成全纳米线的结构; 在多晶硅栅极线的两侧形成硅氧化物侧壁，通过沉积氧化硅膜并随后蚀刻氧化硅膜; 通过离子注入和高温退火形成源极和漏极，从而最终制造出硅纳米线场效应晶体管。该方法与传统的集成电路制造技术相兼容。制造工艺简单方便，循环周期短。

7. 发明申请

US20130011980A1 FABRICATION METHOD OF VERTICAL SILICON NANOWIRE FIELD EFFECT TRANSISTOR 有权
标题翻译：垂直硅纳米管场效应晶体管的制造方法
公开(公告)号：US20130011980A1
公开(公告)日：2013-01-10
申请号：US13501711
申请日：2011-11-18
申请人： Ru Huang , Jiewen Fan , Yujie Ai , Shuai Sun , Runsheng Wang , Jibin Zou , Xin Huang
发明人： Ru Huang , Jiewen Fan , Yujie Ai , Shuai Sun , Runsheng Wang , Jibin Zou , Xin Huang
IPC分类号： H01L21/336 , B82Y40/00
CPC分类号： H01L29/0676 , B82Y10/00 , B82Y40/00 , H01L29/66439 , H01L29/775
摘要： The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.
摘要翻译：本发明公开了一种具有低寄生电阻的垂直硅纳米线场效应晶体管的制造方法，其涉及超大集成电路制造技术的领域。与传统的平面场效应晶体管相比，一方面，本发明制造的垂直硅纳米线场效应晶体管可以提供良好的抑制由于一维结构引起的栅极控制能力的短通道效应的能力，并减少泄漏电流和漏极引起的屏障降低（DIBL）。另一方面，晶体管的面积进一步减小，并且IC系统的集成度增加。

8. 发明授权

US09034702B2 Method for fabricating silicon nanowire field effect transistor based on wet etching 有权
标题翻译：基于湿蚀刻制造硅纳米线场效应晶体管的方法
公开(公告)号：US09034702B2
公开(公告)日：2015-05-19
申请号：US13511123
申请日：2011-11-18
申请人： Ru Huang , Jiewen Fan , Yujie Ai , Shuai Sun , Runsheng Wang , Jibin Zou , Xin Huang
发明人： Ru Huang , Jiewen Fan , Yujie Ai , Shuai Sun , Runsheng Wang , Jibin Zou , Xin Huang
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/66 , H01L29/423 , H01L29/786
CPC分类号： H01L29/66772 , H01L29/42392 , H01L29/78696
摘要： Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching. The method includes defining an active region; depositing a silicon oxide film as a hard mask, forming a pattern of a source and a drain and a fine bar connecting the source and the drain; transferring the pattern on the hard mask to a silicon substrate by performing etching process for the silicon substrate; performing ion implanting; etching the silicon substrate by wet etching, so that the silicon fine bar connecting the source and the drain is suspended; reducing the silicon fine bar to a nano size to form a silicon nanowire; depositing a polysilicon film; forming a polysilicon gate line acrossing the silicon nanowire by electron beam lithography and forming a structure of nanowire-all-around; forming a silicon oxide sidewall at both sides of the polysilicon gate line, by depositing a silicon oxide film and subsequently etching the silicon oxide film; forming the source and the drain by using ion implantation and high temperature annealing, so that the silicon nanowire field effect transistor is finally fabricated. The method is compatible with a conventional integrated circuit fabrication technology. The fabrication process is simple and convenient, and has a short cycle.
摘要翻译：本文公开了一种基于湿蚀刻制造硅纳米线场效应晶体管的方法。该方法包括定义活动区域; 沉积氧化硅膜作为硬掩模，形成源极和漏极的图案以及连接源极和漏极的细棒; 通过对硅衬底进行蚀刻处理，将硬掩模上的图案转移到硅衬底; 进行离子注入; 通过湿蚀刻蚀刻硅衬底，使得连接源极和漏极的硅细棒悬空; 将硅细棒还原成纳米尺寸以形成硅纳米线; 沉积多晶硅膜; 通过电子束光刻形成跨越硅纳米线的多晶硅栅极线，并形成全纳米线的结构; 在多晶硅栅极线的两侧形成硅氧化物侧壁，通过沉积氧化硅膜并随后蚀刻氧化硅膜; 通过离子注入和高温退火形成源极和漏极，从而最终制造出硅纳米线场效应晶体管。该方法与传统的集成电路制造技术相兼容。制造工艺简单方便，循环周期短。

9. 发明授权

US08901644B2 Field effect transistor with a vertical channel and fabrication method thereof 有权
标题翻译：具有垂直沟道的场效应晶体管及其制造方法
公开(公告)号：US08901644B2
公开(公告)日：2014-12-02
申请号：US13821944
申请日：2011-09-09
申请人： Ru Huang , Yujie Ai , Zhihua Hao , Shuangshuang Pu , Jiewen Fan , Shuai Sun , Runsheng Wang , Xiaoyan Xu
发明人： Ru Huang , Yujie Ai , Zhihua Hao , Shuangshuang Pu , Jiewen Fan , Shuai Sun , Runsheng Wang , Xiaoyan Xu
IPC分类号： H01L29/78 , H01L29/66 , H01L29/08 , H01L29/04 , H01L29/775 , H01L29/06 , H01L21/28 , H01L29/41 , H01L29/423
CPC分类号： H01L29/7827 , B82Y10/00 , H01L21/2815 , H01L29/04 , H01L29/0653 , H01L29/0657 , H01L29/0676 , H01L29/0692 , H01L29/0847 , H01L29/413 , H01L29/42376 , H01L29/66439 , H01L29/66666 , H01L29/775
摘要： Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which is formed over a substrate and perpendicular to the substrate; a source, which is made of polysilicon, is located at an upper end of the Si platform; a drain is disposed at an outside of a lower end of the circular ring-shaped Si platform; a gate is placed on an outer side surface of the circular ring-shaped Si platform; and an inside of the circular ring-shaped Si platform is filled with a dielectric material. In comparison with the conventional vertical structure MOSFET with a Si platform, the circular ring-shaped structure field effect transistor according to the invention can effectively suppress the short channel effect and improve the device performance.
摘要翻译：本文公开了具有垂直沟道的场效应晶体管及其制造方法。场效应晶体管的沟道区域是形成在衬底上并垂直于衬底的圆形环形Si平台; 由多晶硅制成的源头位于Si平台的上端; 在圆环状Si平台的下端的外侧配置有排水口，在圆环状Si平台的外侧面上设置有闸门; 并且圆形环形Si平台的内部填充有电介质材料。与传统的具有Si平台的垂直结构MOSFET相比，根据本发明的圆环形结构场效应晶体管可以有效地抑制短沟道效应并提高器件性能。

10. 发明申请

US20130130503A1 METHOD FOR FABRICATING ULTRA-FINE NANOWIRE 审中-公开
标题翻译：制造超细纳米线的方法
公开(公告)号：US20130130503A1
公开(公告)日：2013-05-23
申请号：US13511624
申请日：2012-02-03
申请人： Ru Huang , Shuai Sun , Yujie Ai , Jiewen Fan , Runsheng Wang , Xiaoyan Xu
发明人： Ru Huang , Shuai Sun , Yujie Ai , Jiewen Fan , Runsheng Wang , Xiaoyan Xu
IPC分类号： H01L21/308 , B82Y40/00
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L29/0673
摘要： Disclosed herein is a method for fabricating an ultra-fine nanowire by combining a trimming process and a mask blocking oxidation process. The ultra-thin nanowire is fabricated by a combination of performing a trimming process on a mask to reduce a width of the mask and blocking an oxidation through the mask. A diameter of the floated ultra-thin nanowire fabricated by the method is controlled to 20 nm below by a thickness of a deposited silicon oxide film, a width of the silicon oxide nanowire after trimming, and a time and a temperature for performing a wet oxidation process. Also, since a speed of the wet oxidation process is faster, the width of the nanowire obtained by a conventional photolithography is reduced faster. Moreover, when fabricating an ultra-thin nanowire by using the method, the cost is reduced and it is more feasible to be implemented.
摘要翻译：本文公开了通过组合修整工艺和掩模阻挡氧化工艺来制造超细纳米线的方法。超薄纳米线通过对掩模进行修整处理以减少掩模的宽度并阻挡通过掩模的氧化的组合来制造。通过该方法制造的漂浮的超薄纳米线的直径通过沉积的氧化硅膜的厚度，修整后的氧化硅纳米线的宽度以及进行湿氧化的时间和温度控制在20nm以下处理。此外，由于湿式氧化处理的速度更快，所以通过常规光刻获得的纳米线的宽度更快地降低。此外，当通过使用该方法制造超薄纳米线时，成本降低，并且更可行。

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