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1. 发明申请

US20120302014A1 METHOD FOR FABRICATING SURROUNDING-GATE SILICON NANOWIRE TRANSISTOR WITH AIR SIDEWALLS 有权
标题翻译：用于制造具有空气平台的环形硅纳米晶体管的方法
公开(公告)号：US20120302014A1
公开(公告)日：2012-11-29
申请号：US13384215
申请日：2011-07-04
申请人： Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
发明人： Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/78696 , H01L21/76289 , H01L29/0673 , H01L29/42392 , H01L29/66772
摘要： A method for fabricating a surrounding-gate silicon nanowire transistor with air sidewalls is provided. The method is compatible with the CMOS process; the introduced air sidewalls can reduce the parasitic capacitance effectively and increase the transient response characteristic of the device, thus being applicable to a high-performance logic circuit.
摘要翻译：提供了一种制造具有空气侧壁的环形栅极硅纳米线晶体管的方法。该方法与CMOS工艺兼容; 引入的空气侧壁可以有效地减小寄生电容并增加器件的瞬态响应特性，从而适用于高性能逻辑电路。

2. 发明授权

US08513067B2 Fabrication method for surrounding gate silicon nanowire transistor with air as spacers 有权
标题翻译：围绕栅极硅纳米线晶体管的制造方法，其中空气为间隔物
公开(公告)号：US08513067B2
公开(公告)日：2013-08-20
申请号：US13266791
申请日：2011-07-15
申请人： Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
发明人： Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
IPC分类号： H01L21/84
CPC分类号： H01L29/66439 , B82Y10/00 , H01L29/775
摘要： The invention discloses a fabrication method for a surrounding gate silicon nanowire transistor with air as spacers. The method comprises: performing isolation, and depositing a material A which has a higher etch selectivity ratio with respect to Si; performing photolithography to define a Fin hard mask; etching the material A to form the Fin hard mask; performing source and drain implantation; performing photolithography to define a channel region and large source/drain regions; forming the Si Fin and the large source/drains; removing the hard mask of the material A; forming a nanowire; etching the SiO2 to form a floating nanowire; forming a gate oxide layer; depositing a polysilicon; performing polysilicon injection; performing annealing to activate dopants; etching the polysilicon; depositing SiN; performing photolithography to define a gate pattern; etching the SiN and the polysilicon to form the gate pattern; separating the gate and the source/drain with a space in between filled with air; depositing SiO2 to form air sidewalls; performing annealing to densify the SiO2 layer; using subsequent processes to complete the device fabrication. The invention is compatible with the CMOS process flow. The introduction of the air sidewalls can effectively reduce the parasitic capacitance of the device, and improve the transient response of the device, so that the method is applicable for a logic circuit with high performance.
摘要翻译：本发明公开了一种具有空气作为间隔物的周围栅极硅纳米线晶体管的制造方法。该方法包括：执行隔离和沉积相对于Si具有较高蚀刻选择比的材料A; 执行光刻以限定Fin硬掩模; 蚀刻材料A以形成Fin硬掩模; 进行源极和漏极植入; 执行光刻以限定沟道区和大的源极/漏极区; 形成Si Fin和大源/排水; 去除材料A的硬掩模; 形成纳米线; 蚀刻SiO 2以形成浮动的纳米线; 形成栅氧化层; 沉积多晶硅; 执行多晶硅注入; 执行退火以激活掺杂剂; 蚀刻多晶硅; 沉积SiN; 执行光刻以限定栅极图案; 蚀刻SiN和多晶硅以形成栅极图案; 分离门和源/排水管之间的空间填充空气之间; 沉积SiO 2以形成空气侧壁; 进行退火以使SiO 2层致密化; 使用后续过程来完成器件制造。本发明与CMOS工艺流程兼容。空气侧壁的引入可以有效降低器件的寄生电容，提高器件的瞬态响应，使其适用于具有高性能的逻辑电路。

3. 发明授权

US08563370B2 Method for fabricating surrounding-gate silicon nanowire transistor with air sidewalls 有权
标题翻译：用于制造具有空气侧壁的环形栅极硅纳米线晶体管的方法
公开(公告)号：US08563370B2
公开(公告)日：2013-10-22
申请号：US13384215
申请日：2011-07-04
申请人： Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
发明人： Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
IPC分类号： H01L21/338
CPC分类号： H01L29/78696 , H01L21/76289 , H01L29/0673 , H01L29/42392 , H01L29/66772
摘要： A method for fabricating a surrounding-gate silicon nanowire transistor with air sidewalls is provided. The method is compatible with the CMOS process; the introduced air sidewalls can reduce the parasitic capacitance effectively and increase the transient response characteristic of the device, thus being applicable to a high-performance logic circuit.
摘要翻译：提供了一种制造具有空气侧壁的环形栅极硅纳米线晶体管的方法。该方法与CMOS工艺兼容; 引入的空气侧壁可以有效地减小寄生电容并增加器件的瞬态响应特性，从而适用于高性能逻辑电路。

4. 发明申请

US20130017654A1 FABRICATION METHOD FOR SURROUNDING GATE SILICON NANOWIRE TRANSISTOR WITH AIR AS SPACERS 有权
标题翻译：具有空气作为间隔件的环形硅纳米晶体管的制造方法
公开(公告)号：US20130017654A1
公开(公告)日：2013-01-17
申请号：US13266791
申请日：2011-07-15
申请人： Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
发明人： Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
IPC分类号： H01L21/336 , B82Y99/00
CPC分类号： H01L29/66439 , B82Y10/00 , H01L29/775
摘要： The invention discloses a fabrication method for a surrounding gate silicon nanowire transistor with air as spacers. The method comprises: performing isolation, and depositing a material A which has a higher etch selectivity ratio with respect to Si; performing photolithography to define a Fin hard mask; etching the material A to form the Fin hard mask; performing source and drain implantation; performing photolithography to define a channel region and large source/drain regions; forming the Si Fin and the large source/drains; removing the hard mask of the material A; forming a nanowire; etching the SiO2 to form a floating nanowire; forming a gate oxide layer; depositing a polysilicon; performing polysilicon injection; performing annealing to activate dopants; etching the polysilicon; depositing SiN; performing photolithography to define a gate pattern; etching the SiN and the polysilicon to form the gate pattern; separating the gate and the source/drain with a space in between filled with air; depositing SiO2 to form air sidewalls; performing annealing to densify the SiO2 layer; using subsequent processes to complete the device fabrication. The invention is compatible with the CMOS process flow. The introduction of the air sidewalls can effectively reduce the parasitic capacitance of the device, and improve the transient response of the device, so that the method is applicable for a logic circuit with high performance.
摘要翻译：本发明公开了一种具有空气作为间隔物的周围栅极硅纳米线晶体管的制造方法。该方法包括：执行隔离和沉积相对于Si具有较高蚀刻选择比的材料A; 执行光刻以限定Fin硬掩模; 蚀刻材料A以形成Fin硬掩模; 进行源极和漏极植入; 执行光刻以限定沟道区和大的源极/漏极区; 形成Si Fin和大源/排水; 去除材料A的硬掩模; 形成纳米线; 蚀刻SiO 2以形成浮动的纳米线; 形成栅氧化层; 沉积多晶硅; 执行多晶硅注入; 执行退火以激活掺杂剂; 蚀刻多晶硅; 沉积SiN; 执行光刻以限定栅极图案; 蚀刻SiN和多晶硅以形成栅极图案; 分离门和源/排水管之间的空间填充空气之间; 沉积SiO 2以形成空气侧壁; 进行退火以使SiO 2层致密化; 使用后续过程来完成器件制造。本发明与CMOS工艺流程兼容。空气侧壁的引入可以有效降低器件的寄生电容，提高器件的瞬态响应，使其适用于具有高性能的逻辑电路。

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