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1. 发明授权

US10225196B2 Apparatus, system and method for controlling packet data flow 有权
公开(公告)号：US10225196B2
公开(公告)日：2019-03-05
申请号：US14765841
申请日：2013-02-15
申请人： Roy Shor , Ori Goren , Avraham Horn , John Vaglica , Tuongvu Nguyen
发明人： Roy Shor , Ori Goren , Avraham Horn , John Vaglica , Tuongvu Nguyen
IPC分类号： H04L12/833 , H04L29/08 , H04W72/04
摘要： A system for use in nodes communicating over a CPRI (common public radio interface) allows each networking node in a daisychain configuration to seamlessly manage the control and management HDLC (high-speed data link control) channel for both uplink and downlink. The connection is kept alive through a soft reset flow. Received HDLC packets can be extracted for use by a local node. Locally generated packets can be inserted into the packet data stream at the datalink layer for onward transmission over the CPRI. The system arbitrates between the locally generated packet data held in a buffer in the local node and remote packet data received from a remote node and held in the local node in a first in first out buffer for onward transmission to a subsequent node after arbitration. Remote packet data is given priority.

2. 发明申请

US20160128040A1 METHOD AND DEVICE FOR INTERFACING IN A MOBILE COMMUNICATION SYSTEM 有权
标题翻译：用于在移动通信系统中接口的方法和设备
公开(公告)号：US20160128040A1
公开(公告)日：2016-05-05
申请号：US14889485
申请日：2013-05-29
申请人： Roy Shor , Ori Goren , Avraham Horn
发明人： Roy Shor , Ori Goren , Avraham Horn
IPC分类号： H04W72/04 , H04L27/233
CPC分类号： H04W72/044 , H04L27/2338 , H04W88/085 , H04W88/181 , H04W92/00
摘要： Interfacing according to a common public radio interface in a base station in a mobile communication system is described. The interfacing comprises a conversion process for rate-converting legacy data samples. First a predetermined number of the legacy data samples is converted to frequency samples in a frequency domain, then the frequency samples are zero padded to extend the frequency range according to a related sample rate of a 4G data format and then converted into a number of data samples of the related sample rate. The related sample rate is a multiplication of S/K times a basic frame rate of the 4G data format, S samples being allocated to K frames, K and S being integers and K being 8 or less. Advantageously large buffers for allocating a large number of legacy samples to 4G frames are avoided.
摘要翻译：描述了根据移动通信系统中的基站中的公共无线电接口的公共接口。接口包括用于对传统数据样本进行速率转换的转换过程。首先，将预定数量的遗留数据样本转换为频域中的频率采样，然后根据4G数据格式的相关采样率将频率采样零填充以扩展频率范围，然后转换成多个数据相关采样率样本。相关采样率是S / K乘以4G数据格式的基本帧速率，S个样本被分配给K个帧，K和S是整数，K是8或更小。有利的是，避免了将大量遗留样本分配到4G帧的大型缓冲器。

3. 发明授权

US09635710B2 Method and apparatus for processing data flows 有权
公开(公告)号：US09635710B2
公开(公告)日：2017-04-25
申请号：US14776746
申请日：2013-03-28
申请人： Roy Shor , Ori Goren , Avraham Horn
发明人： Roy Shor , Ori Goren , Avraham Horn
IPC分类号： H04W4/00 , H04W88/08
CPC分类号： H04W88/085
摘要： An apparatus for facilitating the re-distribution of processing load between a plurality of radio equipment controllers arranged in a daisy chain configuration on a Common Public Radio Interface. The apparatus may be included in each REC and has two framers which may co-operate to forward IQ data of antenna carriers received on a downlink from a preceding REC to a subsequent REC in the chain and a DMA module or channel which can read IQ data from a system memory for onward transmission. In a re-allocation mode, the framer may be reconfigured so that an AxC initially allocated to a preceding REC for processing may be instead, accessed by a second (usually redundant) transmit DMA module included in the apparatus from system memory and transferred to the framer for onward transmission.

4. 发明授权

US10342032B2 Method and device for streaming control data in a mobile communication system 有权
公开(公告)号：US10342032B2
公开(公告)日：2019-07-02
申请号：US14899137
申请日：2013-07-04
申请人： Roy Shor , Ori Goren , Avraham Horn , Yael Kahil , Shay Shpritz
发明人： Roy Shor , Ori Goren , Avraham Horn , Yael Kahil , Shay Shpritz
IPC分类号： H04W72/12 , H04W88/08 , H04L12/721
摘要： Interfacing between radio units in a base station in a mobile communication system uses a common public radio interface CPRI for streaming IQ data samples and control data arranged in lanes. A separate serial interface sRIO is now additionally used for transferring selected control data arranged in packets to a controller, the selected control data being streamed between other radio units via the common public radio interface. In the radio unit, the selected control data are arranged in packets to be transmitted via the serial interface, and, vice versa, the selected control data arranged in packets received via the serial interface are arranged in lanes to be streamed. Advantageously the control data of the streaming CPRI interface is seamlessly transferred to the controller via the packet based serial interface.

5. 发明授权

US10334008B2 Method and device for data streaming in a mobile communication system 有权
公开(公告)号：US10334008B2
公开(公告)日：2019-06-25
申请号：US14899132
申请日：2013-07-04
申请人： Roy Shor , Ori Goren , Avraham Horn , Avraham Rabinovich
发明人： Roy Shor , Ori Goren , Avraham Horn , Avraham Rabinovich
IPC分类号： H04L29/06 , H04L29/08 , H04L29/10 , H04W76/00 , H04W88/08
摘要： Interfacing between radio units in a base station in a mobile communication system uses a common public radio interface CPRI for streaming IQ data samples arranged in lanes. A separate serial interface sRIO is now additionally used for transferring selected data samples arranged in packets, the selected samples corresponding to selected lanes streamed between other radio units via the common public radio interface. In the radio unit, the selected data samples are arranged in packets to be transmitted via the serial interface, and, vice versa, the selected data samples arranged in packets received via the serial interface are arranged in lanes. A system timer coupled to the CPRI generates a timebase for controlling the sRIO interface in order to have it synchronized. Advantageously the data sample transfer capacity of the streaming CPRI interface is extended using the packet based serial interface.

6. 发明授权

US09730215B2 Method and device for interfacing in a mobile communication system 有权
公开(公告)号：US09730215B2
公开(公告)日：2017-08-08
申请号：US14889485
申请日：2013-05-29
申请人： Roy Shor , Ori Goren , Avraham Horn
发明人： Roy Shor , Ori Goren , Avraham Horn
IPC分类号： H04W72/04 , H04W88/18 , H04L27/233 , H04W92/00 , H04W88/08
CPC分类号： H04W72/044 , H04L27/2338 , H04W88/085 , H04W88/181 , H04W92/00
摘要： Interfacing according to a common public radio interface in a base station in a mobile communication system is described. The interfacing comprises a conversion process for rate-converting legacy data samples. First a predetermined number of the legacy data samples is converted to frequency samples in a frequency domain, then the frequency samples are zero padded to extend the frequency range according to a related sample rate of a 4G data format and then converted into a number of data samples of the related sample rate. The related sample rate is a multiplication of S/K times a basic frame rate of the 4G data format, S samples being allocated to K frames, K and S being integers and K being 8 or less. Advantageously large buffers for allocating a large number of legacy samples to 4G frames are avoided.

7. 发明授权

US09094908B1 Device and method for synchronization in a mobile communication system 有权
标题翻译：移动通信系统中同步的装置和方法
公开(公告)号：US09094908B1
公开(公告)日：2015-07-28
申请号：US14258394
申请日：2014-04-22
申请人： Roi Menahem Shor , Ori Goren , Avraham Horn
发明人： Roi Menahem Shor , Ori Goren , Avraham Horn
IPC分类号： H04L7/00 , H04W56/00 , H04L7/033
CPC分类号： H04W56/0015 , H04J3/0685
摘要： Interfacing between radio units in a base station in a mobile communication system may use synchronized clocks. A controller device has a tracking clock circuit for generating a transmit clock, the tracking clock circuit comprising a clock input for receiving a reference clock and a sync input for receiving an external synchronization signal. A multiplying phase locked loop generates the transmit clock in dependence on the reference clock and a divider output of a controllable divider coupled to the transmit clock. A tracking loop has a phase detector coupled to the sync input and the divider output for detecting a phase error between the external synchronization signal and transmit clock, and a phase control circuit for generating a phase control signal based on the phase error, the phase control signal being coupled to a control input of the controllable divider for adapting the division function.
摘要翻译：在移动通信系统中的基站中的无线电单元之间的接口可以使用同步的时钟。控制器装置具有用于产生传输时钟的跟踪时钟电路，跟踪时钟电路包括用于接收参考时钟的时钟输入和用于接收外部同步信号的同步输入。乘法锁相环根据参考时钟和耦合到发送时钟的可控分频器的分频器输出产生发送时钟。跟踪环路具有耦合到同步输入的相位检测器和用于检测外部同步信号和发送时钟之间的相位误差的分频器输出端，以及用于基于相位误差产生相位控制信号的相位控制电路，相位控制信号耦合到可控分频器的控制输入端，以适应分频功能。

8. 发明授权

US09521636B2 Synchronization circuitry, common public radio interface enable device, and a method of synchronizing a synchronized clock signal of a second transceiver to a clock of a first transceiver 有权
标题翻译：同步电路，公共无线电接口使能装置，以及将第二收发器的同步时钟信号同步到第一收发机的时钟的方法
公开(公告)号：US09521636B2
公开(公告)日：2016-12-13
申请号：US14258415
申请日：2014-04-22
申请人： Roi Menahem Shor , Ori Goren , Avraham Horn
发明人： Roi Menahem Shor , Ori Goren , Avraham Horn
IPC分类号： H04W56/00 , H04L7/033
CPC分类号： H04W56/001 , H04L7/033 , H04L7/0331
摘要： A controller device can control the time of a slave sub-system in a chain in a base station system. The controller device comprises a slave transceiver for receiving/transmitting from/to a master sub-system, and a synchronization device for synchronizing a clock of the slave transceiver to a clock of the master sub-system based on the received signal received from the master sub-system. The synchronization circuitry comprises a clock input port for receiving an external clock signal from an external clock generator. At a received signal input port the received signal can be received from the master transceiver. A tracking loop couples the received signal input and the second phase input to a control input of a controllable PLL, for providing a negative feedback which controls a phase and/or frequency of the feedback signal to counter the phase and or frequency error between the external clock signal and the received signal.
摘要翻译：控制器设备可以控制从站子系统在基站系统链中的时间。控制器设备包括用于从主子系统接收/发送的从收发器，以及同步设备，用于基于从主设备接收的接收信号将从属收发器的时钟同步到主子系统的时钟子系统。同步电路包括用于从外部时钟发生器接收外部时钟信号的时钟输入端口。在接收到的信号输入端口，可以从主收发器接收接收到的信号。跟踪环路将接收信号输入和第二相输入耦合到可控PLL的控制输入，用于提供负反馈，该反馈控制反馈信号的相位和/或频率以抵消外部的相位和/或频率误差时钟信号和接收信号。

9. 发明授权

US09824044B2 Common public radio interface (CPRI) lane controller coupled to direct memory access (DMA) wherein a time division duplex (TDD) steers control of CPRI 有权
公开(公告)号：US09824044B2
公开(公告)日：2017-11-21
申请号：US14759203
申请日：2013-01-10
申请人： Roy Shor , Nir Baruch , Ori Goren , Amit Gur
发明人： Roy Shor , Nir Baruch , Ori Goren , Amit Gur
IPC分类号： G06F13/28 , G06F13/42 , G06F13/24 , H04W88/08
CPC分类号： G06F13/287 , G06F13/24 , G06F13/4282 , H04W88/085
摘要： A Common Public Radio Interface, CPRI, lane controller of a processor, in a Time Division Duplex, TDD, system, said CPRI lane controller comprising: a Direct Memory Access (or more than one), DMA, controller connected to a memory through a switch fabric to perform read or/and write memory access transactions via an internal system bus of said processor, wherein said DMA controller is adapted to generate a RX/TX transaction interrupt(s) for each completed memory access RX/TX transaction counted by a corresponding transaction counter(s) which provides a TDD slot awareness interrupt(s) when a RX/TX TDD slot has terminated, wherein said DMA controller has a steering control(s) adapted to steer the memory access transactions either to said memory or to be legitimately blocked by said switch fabric in response to said TDD slot awareness interrupt(s) to save bandwidth, BW, of the internal system bus of said processor.

10. 发明授权

US09935873B2 Device and method for processing in a mobile communication system 有权
公开(公告)号：US09935873B2
公开(公告)日：2018-04-03
申请号：US14895949
申请日：2013-06-18
申请人： Roy Shor , Ori Goren , Amit Gur , Gad Yuval
发明人： Roy Shor , Ori Goren , Amit Gur , Gad Yuval
IPC分类号： H04L12/721 , H04L12/861 , H04L12/64
CPC分类号： H04L45/38 , H04L12/6418 , H04L49/90 , H04L49/9078
摘要： A processor device processes data samples of a radio signal in a mobile communication system. A fast flow process is executed for all samples and a batch process is executed at intervals on a subset of the samples. The device has a processor for executing the flow process via a local buffer memory, a memory interface to a system memory, and a memory controller for controlling storing of the data samples in the buffer memory. The processor establishes whether data samples in the local buffer memory are part of the subset, and if not, invalidates them after executing the flow process. The memory controller provides free memory space in the local buffer by transferring data samples which are not invalidated from the local buffer memory to the system memory, and by invalidating processed samples. Advantageously the local buffer may be relatively small, while the amount of data transferred to the system memory is limited.

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