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1. 发明申请

US20150028948A1 SWITCH-MODE AMPLIFIER 有权
标题翻译：开关式放大器
公开(公告)号：US20150028948A1
公开(公告)日：2015-01-29
申请号：US13953597
申请日：2013-07-29
申请人： Joseph Staudinger , Paul Hart , Ramanujam Srinidhi Embar , John Vaglica
发明人： Joseph Staudinger , Paul Hart , Ramanujam Srinidhi Embar , John Vaglica
IPC分类号： H03F3/217
CPC分类号： H03F3/2171 , H03F1/0288
摘要： A device includes a Doherty amplifier. The Doherty amplifier has a carrier path and a peaking path. The Doherty amplifier includes a carrier amplifier configured to amplify a signal received from the carrier path and a peaking amplifier configured to amplify a signal received from the peaking path. The device includes a resistive switch having a first terminal connected to the peaking path and a second terminal connected to a voltage reference, and a controller configured to set the resistive switch to a first resistance value when a power input of the Doherty amplifier is below a threshold and to a second resistance value when the power input of the Doherty amplifier is above the threshold.
摘要翻译：一个器件包括一个Doherty放大器。 Doherty放大器具有载波路径和峰值路径。多赫蒂放大器包括被配置为放大从载波路径接收的信号的载波放大器和配置成放大从峰值路径接收的信号的峰值放大器。该装置包括具有连接到峰化路径的第一端子和连接到电压基准的第二端子的电阻开关，以及控制器，其被配置为当Doherty放大器的功率输入低于一个时，将该电阻开关设置为第一电阻值当Doherty放大器的功率输入高于阈值时，阈值和第二电阻值。

2. 发明申请

US20070088889A1 COMMUNICATION STEERING FOR USE IN A MULTI-MASTER SHARED RESOURCE SYSTEM 有权
标题翻译：用于多主共享资源系统的通信方向
公开(公告)号：US20070088889A1
公开(公告)日：2007-04-19
申请号：US11610956
申请日：2006-12-14
申请人： Arnaldo Cruz , John Vaglica , William Moyer , Tuongvu Nguyen
发明人： Arnaldo Cruz , John Vaglica , William Moyer , Tuongvu Nguyen
IPC分类号： G06F13/24
CPC分类号： G06F13/385 , G06F13/24 , G06F2213/0042
摘要： New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.
摘要翻译：需要用于在多个主机（12,14）和一个或多个共享资源（24,30,100）之间提供通信的新方法。可能需要共享的资源的一个例子是符合通用串行总线（USB）标准（100）的电路。 USB规范将USB端点定义为位于USB设备中的数据和控制通道。在一些情况下，期望具有由一个处理器控制的一定数量的端点以及由不同处理器控制的其他端点，从而提供对所有端点的共享控制。电路（402,417,480）可用于为诸如中断的附加信号提供转向。其他共享资源（24,30）可以使用更集中的电路（36）来执行附加信号的转向功能。

3. 发明申请

US20050265507A1 Method and system for employing adaptive event codes 有权
标题翻译：采用自适应事件代码的方法和系统
公开(公告)号：US20050265507A1
公开(公告)日：2005-12-01
申请号：US10747844
申请日：2003-12-29
申请人： Charbel Khawand , Jianping Tao , John Vaglica
发明人： Charbel Khawand , Jianping Tao , John Vaglica
IPC分类号： H04J3/06 , H04L7/00 , H04L23/00
CPC分类号： G06F9/542
摘要： The invention concerns a method (500) for employing adaptive event codes. The method includes the steps of generating (512) at least one adaptive event code in which the adaptive event code corresponds to a preexisting event code, storing (514) the adaptive event code in at least one table (154, 156), running (516) the table in which the adaptive event codes are at least initially disabled and enabling (522) the adaptive event code in response to a system event in which the preexisting event code that corresponds to the enabled adaptive event code is executed (526). The method can further include the step of ignoring (518) the adaptive event codes during the running step when the adaptive event codes are disabled.
摘要翻译：本发明涉及一种采用自适应事件代码的方法（500）。该方法包括以下步骤：产生（512）至少一个自适应事件代码，其中自适应事件代码对应于预先存在的事件代码，将自适应事件代码存储在至少一个表（154,156）中，运行（ 516）响应于其中执行与启用的自适应事件代码相对应的预先存在的事件代码的系统事件，启用（522）自适应事件代码（526），其中自适应事件代码至少被初始禁用的表（526）。该方法还可以包括当禁用自适应事件代码时在运行步骤期间忽略（518）自适应事件代码的步骤。

4. 发明申请

US20050080961A1 Communication steering for use in a multi-master shared resource system 审中-公开
公开(公告)号：US20050080961A1
公开(公告)日：2005-04-14
申请号：US10682571
申请日：2003-10-09
申请人： Ryan Bedwell , Arnaldo Cruz , John Vaglica , William Moyer
发明人： Ryan Bedwell , Arnaldo Cruz , John Vaglica , William Moyer
IPC分类号： G06F20060101 , G06F13/36 , G06F13/364
CPC分类号： G06F13/364
摘要： New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.

5. 发明授权

US09136804B2 Switch-mode amplifier 有权
标题翻译：开关模式放大器
公开(公告)号：US09136804B2
公开(公告)日：2015-09-15
申请号：US13953597
申请日：2013-07-29
申请人： Joseph Staudinger , Paul Hart , Ramanujam Srinidhi Embar , John Vaglica
发明人： Joseph Staudinger , Paul Hart , Ramanujam Srinidhi Embar , John Vaglica
IPC分类号： H03F1/07 , H03F3/217
CPC分类号： H03F3/2171 , H03F1/0288
摘要： A device includes a Doherty amplifier. The Doherty amplifier has a carrier path and a peaking path. The Doherty amplifier includes a carrier amplifier configured to amplify a signal received from the carrier path and a peaking amplifier configured to amplify a signal received from the peaking path. The device includes a resistive switch having a first terminal connected to the peaking path and a second terminal connected to a voltage reference, and a controller configured to set the resistive switch to a first resistance value when a power input of the Doherty amplifier is below a threshold and to a second resistance value when the power input of the Doherty amplifier is above the threshold.
摘要翻译：一个器件包括一个Doherty放大器。 Doherty放大器具有载波路径和峰值路径。多赫蒂放大器包括被配置为放大从载波路径接收的信号的载波放大器和配置成放大从峰值路径接收的信号的峰值放大器。该装置包括具有连接到峰化路径的第一端子和连接到电压基准的第二端子的电阻开关，以及控制器，其被配置为当Doherty放大器的功率输入低于一个时，将该电阻开关设置为第一电阻值当Doherty放大器的功率输入高于阈值时，阈值和第二电阻值。

6. 发明申请

US20050080975A1 Data processing system having a serial data controller 有权
标题翻译：数据处理系统具有串行数据控制器
公开(公告)号：US20050080975A1
公开(公告)日：2005-04-14
申请号：US10683778
申请日：2003-10-10
申请人： Mark Elledge , John Vaglica , Sreedharan Bhaskaran , Allen Deng
发明人： Mark Elledge , John Vaglica , Sreedharan Bhaskaran , Allen Deng
IPC分类号： G06F20060101 , G06F13/00 , G06F13/40
CPC分类号： G06F13/4027 , Y02D10/14 , Y02D10/151
摘要： A data processing system (30) includes two processors (70, 80) and a serial data controller (36) for selectively multiplexing serial data signals between one or more of a plurality of serial data devices (40, 42, 44, 46, 74, 76, 82) The serial data controller (36) includes one or more host ports (50, 52, 54) and one or more peripheral ports (56, 58, 60, 62) coupled together through a switching matrix (64). A control circuit (66) and a plurality of control registers (68) are used to configure and control a serial data path created between two or more ports including clock and frame synchronization timing of the data path.
摘要翻译：数据处理系统（30）包括两个处理器（70,80）和串行数据控制器（36），用于在多个串行数据设备（40,42,44,46,74）中的一个或多个串行数据设备串行数据控制器（36）包括通过交换矩阵（64）耦合在一起的一个或多个主机端口（50,52,54）和一个或多个外围端口（56,58,60,62）。控制电路（66）和多个控制寄存器（68）用于配置和控制在包括数据路径的时钟和帧同步定时的两个或多个端口之间创建的串行数据路径。

7. 发明申请

US20050079889A1 Cellular modem processing 有权
标题翻译：蜂窝式调制解调器处理
公开(公告)号：US20050079889A1
公开(公告)日：2005-04-14
申请号：US10682746
申请日：2003-10-09
申请人： John Vaglica , Christopher Chun , Jose Corleto-Mena , Arnaldo Cruz , Jianping Tao , Mieu Vu , Mark Elledge , Charbel Khawand , Arthur Goldberg , David Hayes
发明人： John Vaglica , Christopher Chun , Jose Corleto-Mena , Arnaldo Cruz , Jianping Tao , Mieu Vu , Mark Elledge , Charbel Khawand , Arthur Goldberg , David Hayes
IPC分类号： H04M11/00 , H04W84/08 , H04B1/38
CPC分类号： H04W84/08
摘要： A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times
摘要翻译：包括调制解调器处理器和存储器的蜂窝移动站。存储器包括用于调制解调器处理器执行第1层处理器操作，第2层处理器操作和第3层处理器操作的指令。调制解调器处理器执行指令，以便根据蜂窝通信协议对蜂窝移动站执行通信数据的处理器操作。在一个示例中，移动站包括不同级别的存储器以提供不同的确定性访问时间

8. 发明申请

US20050068799A1 Integrated circuit power management for reducing leakage current in circuit arrays and method therefor 有权
公开(公告)号：US20050068799A1
公开(公告)日：2005-03-31
申请号：US10675005
申请日：2003-09-30
申请人： Ryan Bedwell , Christopher Chun , Qadeer Qureshi , John Vaglica
发明人： Ryan Bedwell , Christopher Chun , Qadeer Qureshi , John Vaglica
IPC分类号： G06F1/32 , G11C5/14 , G11C7/22 , G11C7/00 , G11C5/06
CPC分类号： G06F1/3275 , G06F1/3203 , G11C5/14 , G11C7/22 , G11C2207/2227 , Y02D10/14
摘要： Leakage current is eliminated in a memory array during a low power mode of a processing system having a processor that interfaces with the memory array. Because two power planes are created, the processor may continue executing instructions using a system memory while bypassing the memory array when the array is powered down. A switch selectively removes electrical connectivity to a supply voltage terminal in response to either processor-initiated control resulting from execution of an instruction or from a source originating in the system somewhere else than the processor. Upon restoration of power to the memory array, data may or may not need to be marked as unusable depending upon which of the two power planes supporting arrays to the memory array are located. Predetermined criteria may be used to control the timing of the restoration of power. Multiple arrays may be implemented to independently reduce leakage current.

9. 发明申请

US20050021911A1 Method and apparatus for selecting cache ways available for replacement 有权
标题翻译：用于选择可用于替换的缓存方式的方法和装置
公开(公告)号：US20050021911A1
公开(公告)日：2005-01-27
申请号：US10627559
申请日：2003-07-25
申请人： William Moyer , John Vaglica
发明人： William Moyer , John Vaglica
IPC分类号： G06F12/12 , G06F12/00
CPC分类号： G06F12/121 , G06F12/126 , Y02D10/13
摘要： In a multi-way cache, a method for selecting N ways available for replacement includes providing a plurality of rulesets where each one of the plurality of rulesets specifies N ways in the cache that are available for replacement (where N is equal to or greater than zero). The method further includes receiving an access address, and using at least a portion of the access address to select one of the plurality of rulesets. The selected one of the plurality of rulesets may then be used to select N ways in that cache that are available for replacement. One embodiment uses the high order bits of the access address to select a ruleset. An alternate embodiment uses at least a portion of the access address and a ruleset selector control register to select the ruleset. Yet another embodiment uses the access address and address range comparators to select the ruleset.
摘要翻译：在多路缓存中，用于选择可用于替换的N种方式的方法包括提供多个规则集，其中多个规则集中的每一个规则集中的每一个在高速缓存中指定可用于替换的N个路径（其中N等于或大于零）。所述方法还包括接收访问地址，并且使用所述访问地址的至少一部分来选择所述多个规则集中的一个。然后可以使用多个规则集中的所选择的一个来选择可用于替换的高速缓存中的N种方式。一个实施例使用访问地址的高位来选择规则集。替代实施例使用访问地址的至少一部分和规则集选择器控制寄存器来选择规则集。另一个实施例使用访问地址和地址范围比较器来选择规则集。

10. 发明申请

US20150372930A1 APPARATUS, SYSTEM AND METHOD FOR CONTROLLING PACKET DATA FLOW 审中-公开
标题翻译：用于控制分组数据流的装置，系统和方法
公开(公告)号：US20150372930A1
公开(公告)日：2015-12-24
申请号：US14765841
申请日：2013-02-15
申请人： Roy SHOR , Ori GOREN , Avraham HORN , John VAGLICA , Tuongvu NGUYEN
发明人： ROY SHOR , ORI GOREN , AVRAHAM HORN , JOHN VAGLICA , TUONGVU NGUYEN
IPC分类号： H04L12/833 , H04L29/08 , H04W72/04
CPC分类号： H04L47/2458 , H04L69/324 , H04W72/04
摘要： A system for use in nodes communicating over a CPRI (common public radio interface) allows each networking node in a daisychain configuration to seamlessly manage the control and management HDLC (high-speed data link control) channel for both uplink and downlink. The connection is kept alive through a soft reset flow. Received HDLC packets can be extracted for use by a local node. Locally generated packets can be inserted into the packet data stream at the datalink layer for onward transmission over the CPRI. The system arbitrates between the locally generated packet data held in a buffer in the local node and remote packet data received from a remote node and held in the local node in a first in first out buffer for onward transmission to a subsequent node after arbitration. Remote packet data is given priority.
摘要翻译：用于通过CPRI（公共无线电接口）通信的节点的系统允许以菊花链配置的每个网络节点无缝地管理用于上行链路和下行链路的控制和管理HDLC（高速数据链路控制）信道。连接通过软复位流保持活动。接收到的HDLC数据包可以被提取以供本地节点使用。本地生成的数据包可以插入到数据链路层的数据包数据流中，以便通过CPRI向前传输。系统在保存在本地节点的缓冲器中的本地产生的分组数据和从远程节点接收并保存在本地节点中的第一先进先出缓冲器中的本地产生的分组数据之间进行仲裁，以在仲裁之后向后发送到后续节点。远程分组数据优先。

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