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1. 发明授权

US08922224B2 Snoop detection on calibrated bus 有权
标题翻译：校准总线上的监听检测
公开(公告)号：US08922224B2
公开(公告)日：2014-12-30
申请号：US13568557
申请日：2012-08-07
申请人： Ronald L. Billau , Roger J. Gravrok , Brian G. Holthaus , Darryl Solie
发明人： Ronald L. Billau , Roger J. Gravrok , Brian G. Holthaus , Darryl Solie
IPC分类号： G01R35/00
CPC分类号： G06F21/606
摘要： An electronic system having a high speed signaling bus requiring training (calibration) of a calibrated item in a driver circuitry or a receiver circuitry for reliable operation. At manufacturing or in a secure location, secure calibration coefficients are determined for the electronic system and are stored in a non-volatile storage. During operation, the high speed signaling bus may be re-calibrated, resulting in a new currently active calibration coefficient for the calibrated item. A coefficient watchdog checks a new coefficient value selected by the re-calibration at present environmental conditions such as voltage and temperature against the secure calibration coefficients. If the new calibration coefficient value is the same as a calibration coefficient value in an acceptably close secure calibration coefficient, the new calibration coefficient is accepted; if not, a potentially probed warning is created by the coefficient watchdog.
摘要翻译：一种具有高速信号总线的电子系统，其需要在驱动器电路或用于可靠操作的接收机电路中校准的项目进行训练（校准）。在制造或安全的位置，为电子系统确定安全的校准系数，并存储在非易失性存储器中。在操作期间，高速信号总线可以被重新校准，导致校准项目的新的当前活动的校准系数。系数看门狗会根据当前的环境条件（如电压和温度），根据安全校准系数检查通过重新校准选择的新系数值。如果新的校准系数值与可靠的安全校准系数中的校准系数值相同，则接受新的校准系数; 如果没有，系统看门狗会创建潜在的探测警告。

2. 发明申请

US20140043042A1 Snoop Detection on Calibrated Bus 有权
标题翻译：校准总线上的侦测侦测
公开(公告)号：US20140043042A1
公开(公告)日：2014-02-13
申请号：US13568557
申请日：2012-08-07
申请人： Ronald L. Billau , Roger J. Gravrok , Brian G. Holthaus , Darryl Solie
发明人： Ronald L. Billau , Roger J. Gravrok , Brian G. Holthaus , Darryl Solie
IPC分类号： G01R29/00
CPC分类号： G06F21/606
摘要： An electronic system having a high speed signaling bus requiring training (calibration) of a calibrated item in a driver circuitry or a receiver circuitry for reliable operation. At manufacturing or in a secure location, secure calibration coefficients are determined for the electronic system and are stored in a non-volatile storage. During operation, the high speed signaling bus may be re-calibrated, resulting in a new currently active calibration coefficient for the calibrated item. A coefficient watchdog checks a new coefficient value selected by the re-calibration at present environmental conditions such as voltage and temperature against the secure calibration coefficients. If the new calibration coefficient value is the same as a calibration coefficient value in an acceptably close secure calibration coefficient, the new calibration coefficient is accepted; if not, a potentially probed warning is created by the coefficient watchdog.
摘要翻译：一种具有高速信号总线的电子系统，其需要在驱动器电路或用于可靠操作的接收机电路中校准的项目进行训练（校准）。在制造或安全的位置，为电子系统确定安全的校准系数，并存储在非易失性存储器中。在操作期间，高速信号总线可以被重新校准，导致校准项目的新的当前活动的校准系数。系数看门狗会根据当前的环境条件（如电压和温度），根据安全校准系数检查通过重新校准选择的新系数值。如果新的校准系数值与可靠的安全校准系数中的校准系数值相同，则接受新的校准系数; 如果没有，系统看门狗会创建潜在的探测警告。

3. 发明申请

US20090063894A1 Autonomic PCI Express Hardware Detection and Failover Mechanism 审中-公开
标题翻译：自动PCI Express硬件检测和故障转移机制
公开(公告)号：US20090063894A1
公开(公告)日：2009-03-05
申请号：US11846783
申请日：2007-08-29
申请人： Ronald L. Billau , John D. Folkerts , Ross L. Franke , James S. Harveland , Brian G. Holthaus
发明人： Ronald L. Billau , John D. Folkerts , Ross L. Franke , James S. Harveland , Brian G. Holthaus
IPC分类号： G06F11/07 , G06F13/00 , G06F13/14
CPC分类号： G06F13/4282 , G06F11/2005 , G06F2213/0026
摘要： A system with an autonomic PCI Express hardware detection and failover mechanism includes a plurality of combination root complex capable and endpoint capable devices. A combination root complex capable and endpoint capable device may be selectively configured to operate in either a root complex mode or an endpoint mode. One of the devices assumes the root complex mode and the remaining devices each assume the endpoint mode. Each of the endpoint mode devices is adapted to detect a failure of the root complex mode device. In response to detection of the failure of the root complex mode device, one of the endpoint mode devices assumes root complex mode. An endpoint device may include a timer with a timeout value. Whenever, an endpoint device receives a communication from the root complex device, the endpoint device restarts its timer. If the timer times out with the endpoint device receiving a communication from the root complex device, the endpoint device issues a read request to the root complex device. If the root complex device does not respond to the read request, the endpoint device assumes root complex mode. Different endpoint devices may be assigned different timeout values. Accordingly, the endpoint device that is assigned the shortest time out value will assume root complex mode upon detection of a root complex device failure.
摘要翻译：具有自主PCI Express硬件检测和故障转移机制的系统包括多个具有组合根复合能力和端点能力的设备。可以选择性地将具有能力和端点的组合的根复合能力设备配置为在根复合模式或端点模式中操作。其中一个设备假定根复合模式，其余的设备都采用端点模式。端点模式设备中的每一个适于检测根复合模式设备的故障。响应于检测到根复杂模式设备的故障，端点模式设备之一呈现根复合模式。端点设备可以包括具有超时值的定时器。每当端点设备从根复杂设备接收到通信时，端点设备重启其定时器。如果定时器超时，端点设备从根复杂设备接收通信，则端点设备向根配置设备发出读请求。如果根配置设备不响应读请求，则端点设备将采用根复合模式。可以为不同的端点设备分配不同的超时值。因此，在检测到根复杂设备故障时，分配有最短超时值的端点设备将呈现根复合模式。

4. 发明授权

US08843688B2 Concurrent repair of PCIE switch units in a tightly-coupled, multi-switch, multi-adapter, multi-host distributed system 有权
标题翻译：在紧耦合，多开关，多适配器，多主机分布式系统中并行修复PCIE交换机单元
公开(公告)号：US08843688B2
公开(公告)日：2014-09-23
申请号：US13609561
申请日：2012-09-11
申请人： David R. Engebretsen , Brian G. Holthaus , Jonathan L. Kaus , Eric G. Thiemann , Robert W. Todd
发明人： David R. Engebretsen , Brian G. Holthaus , Jonathan L. Kaus , Eric G. Thiemann , Robert W. Todd
IPC分类号： G06F13/40 , G06F9/44 , G06F13/42
CPC分类号： G06F13/4022 , G06F9/4411 , G06F13/4221 , G06F2213/0026 , G06F2213/0058
摘要： Techniques are disclosed to perform an operation to facilitate concurrent repair of PCIe switch units in processing environments such as a tightly coupled, multi-switch, multi-adapter, multi-host distributed system. The operation, for an identified switch unit to be repaired, reconfigures all switch unit hardware in the switch fabric by removing all upstream to downstream connections utilizing the identified switch unit. Connections to hosts via the upstream ports are also removed by the operation. Once the switch unit is powered back on, the operation reconfigures all switch unit hardware in the switch fabric by adding all upstream to downstream connections utilizing the identified switch unit. The operation further restores connections to hosts via the upstream ports.
摘要翻译：披露了技术来执行操作以促进在诸如紧耦合，多开关，多适配器，多主机分布式系统的处理环境中的PCIe交换单元的并发修复。对于要修复的识别的开关单元的操作，通过利用所识别的开关单元去除所有上游到下游连接来重新配置交换结构中的所有交换机单元硬件。通过上游端口与主机的连接也被操作删除。一旦开关单元重新接通，操作通过使用识别的开关单元添加所有上游到下游连接来重新配置交换结构中的所有交换机单元硬件。该操作进一步通过上游端口恢复到主机的连接。

5. 发明申请

US20140075068A1 CONCURRENT REPAIR OF PCIE SWITCH UNITS IN A TIGHTLY-COUPLED, MULTI-SWITCH, MULTI-ADAPTER, MULTI-HOST DISTRIBUTED SYSTEM 有权
标题翻译：紧急连接，多开关，多适配器，多主机分配系统中PCIE开关单元的并行维修
公开(公告)号：US20140075068A1
公开(公告)日：2014-03-13
申请号：US13609561
申请日：2012-09-11
申请人： David R. Engebretsen , Brian G. Holthaus , Jonathan L. Kaus , Eric G. Thiemann , Robert W. Todd
发明人： David R. Engebretsen , Brian G. Holthaus , Jonathan L. Kaus , Eric G. Thiemann , Robert W. Todd
IPC分类号： G06F13/42
CPC分类号： G06F13/4022 , G06F9/4411 , G06F13/4221 , G06F2213/0026 , G06F2213/0058
摘要： Techniques are disclosed to perform an operation to facilitate concurrent repair of PCIe switch units in processing environments such as a tightly coupled, multi-switch, multi-adapter, multi-host distributed system. The operation, for an identified switch unit to be repaired, reconfigures all switch unit hardware in the switch fabric by removing all upstream to downstream connections utilizing the identified switch unit. Connections to hosts via the upstream ports are also removed by the operation. Once the switch unit is powered back on, the operation reconfigures all switch unit hardware in the switch fabric by adding all upstream to downstream connections utilizing the identified switch unit. The operation further restores connections to hosts via the upstream ports.
摘要翻译：披露了技术来执行操作以促进在诸如紧耦合，多开关，多适配器，多主机分布式系统的处理环境中的PCIe交换单元的并发修复。对于要修复的识别的开关单元的操作，通过利用所识别的开关单元去除所有上游到下游连接来重新配置交换结构中的所有交换机单元硬件。通过上游端口与主机的连接也被操作删除。一旦开关单元重新接通，操作通过使用识别的开关单元添加所有上游到下游连接来重新配置交换结构中的所有交换机单元硬件。该操作进一步通过上游端口恢复到主机的连接。

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