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1. 发明申请

US20050086628A1 Method of extracting properties of back end of line (BEOL) chip architecture 失效
标题翻译：提取后端（BEOL）芯片架构性能的方法
公开(公告)号：US20050086628A1
公开(公告)日：2005-04-21
申请号：US10687475
申请日：2003-10-16
申请人： Ronald Filippi , Giovanni Fiorenza , Xiao Liu , Conal Murray , Gregory Northrop , Thomas Shaw , Richard Wachnik , Mary Yvonne Wisniewski
发明人： Ronald Filippi , Giovanni Fiorenza , Xiao Liu , Conal Murray , Gregory Northrop , Thomas Shaw , Richard Wachnik , Mary Yvonne Wisniewski
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5018
摘要： A method for analyzing circuit designs includes discretizing a design representation into pixel elements representative of a structure in the design and determining at least one property for each pixel element representing a portion of the design. Then, a response of the design is determined due to local properties across the design.
摘要翻译：用于分析电路设计的方法包括将设计表示离散成代表设计中的结构的像素元素，并且为表示设计的一部分的每个像素元素确定至少一个属性。然后，由于设计中的局部属性，确定了设计的响应。

2. 发明申请

US20070111510A1 DUAL DAMASCENE MULTI-LEVEL METALLIZATION 有权
标题翻译：双重DAMASCENE多级金属化
公开(公告)号：US20070111510A1
公开(公告)日：2007-05-17
申请号：US11619748
申请日：2007-01-04
申请人： Birendra Agarwala , Eric Coker , Anthony Correale , Hazara Rathore , Timothy Sullivan , Richard Wachnik
发明人： Birendra Agarwala , Eric Coker , Anthony Correale , Hazara Rathore , Timothy Sullivan , Richard Wachnik
IPC分类号： H01L21/4763
CPC分类号： H01L21/76852 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure, comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.
摘要翻译：一种互连结构，包括：具有侧面和底部的下层导线，所述下层导线包括：下芯导体和下导电衬垫，所述下层导线的侧面和底部上的下导电衬垫; 具有侧面和底部的上部电线，所述上部电线包括上部芯导体和上部导电衬垫，所述上部导电衬垫位于所述上部电线的侧面和底部; 并且上导电衬套与下芯体导体接触并且还与衬套到衬垫接触区域中的下导电衬套接触。

3. 发明申请

US20060157788A1 SRAM memories and microprocessors having logic portions implemented in high-performance silicon substrates and SRAM array portions having field effect transistors with linked bodies and methods for making same 有权
标题翻译：具有在高性能硅衬底中实现的逻辑部分的SRAM存储器和微处理器以及具有连接体的场效应晶体管的SRAM阵列部分及其制造方法
公开(公告)号：US20060157788A1
公开(公告)日：2006-07-20
申请号：US11038593
申请日：2005-01-19
申请人： Rajiv Joshi , Richard Wachnik , Yue Tan , Kerry Bernstein
发明人： Rajiv Joshi , Richard Wachnik , Yue Tan , Kerry Bernstein
IPC分类号： H01L27/12 , H01L27/01
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0207 , H01L27/1104
摘要： The present invention generally concerns fabrication methods and device architectures for use in memory circuits, and more particularly concerns hybrid silicon-on-insulator (SOI) and bulk architectures for use in memory circuits. Once aspect of the invention concerns CMOS SRAM cell architectures where at least one pair of adjacent NFETs in an SRAM cell have body regions linked by a leakage path diffusion region positioned beneath shallow source/drain diffusions, where the leakage path diffusion region extends from the bottom of the source/drain diffusion to the buried oxide layer, and at least one pair of NFETs from adjacent SRAM cells which have body regions linked by a similar leakage path diffusion region beneath adjacent source/drain diffusions. Another aspect of this invention concerns a microprocessor fabricated on an hybrid orientation substrate where the logic portion of the circuit has NFETs fabricated in (100) crystal orientation SOI silicon regions with floating body regions and PFETs fabricated in (110) crystal orientation bulk silicon regions; and where the SRAM memory portion has NFETs fabricated in (100) crystal orientation SOI silicon regions with body regions linked by leakage path diffusion regions beneath shallow source/drain diffusions and PFETs fabricated in (110) crystal orientation silicon regions.
摘要翻译：本发明一般涉及用于存储器电路的制造方法和器件架构，更具体地说，涉及用于存储器电路的混合绝缘体上硅（SOI）和批量结构。本发明的一个方面涉及SRAM SRAM单元结构，其中SRAM单元中的至少一对相邻NFET具有通过位于浅源/漏扩散之下的泄漏路径扩散区连接的体区，其中泄漏路径扩散区从底部延伸源极/漏极扩散到掩埋氧化物层的至少一对NFET，以及来自相邻SRAM单元的至少一对NFET，其具有通过相邻的源极/漏极扩散附近的相似泄漏路径扩散区域连接的体区。本发明的另一方面涉及一种制造在混合取向基板上的微处理器，其中该电路的逻辑部分具有在具有浮动体区域的（100）晶体取向SOI硅区域和在（110）晶体取向体硅区域中制造的PFET）制造的NFET。并且其中SRAM存储器部分具有在（100）晶体取向SOI硅区域中制造的NFET，其中主体区域通过在（110）晶体取向硅区域中制造的浅源/漏扩散下的泄漏路径扩散区域和PFET连接。

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