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1. 发明申请

US20070111510A1 DUAL DAMASCENE MULTI-LEVEL METALLIZATION 有权
标题翻译：双重DAMASCENE多级金属化
公开(公告)号：US20070111510A1
公开(公告)日：2007-05-17
申请号：US11619748
申请日：2007-01-04
申请人： Birendra Agarwala , Eric Coker , Anthony Correale , Hazara Rathore , Timothy Sullivan , Richard Wachnik
发明人： Birendra Agarwala , Eric Coker , Anthony Correale , Hazara Rathore , Timothy Sullivan , Richard Wachnik
IPC分类号： H01L21/4763
CPC分类号： H01L21/76852 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure, comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.
摘要翻译：一种互连结构，包括：具有侧面和底部的下层导线，所述下层导线包括：下芯导体和下导电衬垫，所述下层导线的侧面和底部上的下导电衬垫; 具有侧面和底部的上部电线，所述上部电线包括上部芯导体和上部导电衬垫，所述上部导电衬垫位于所述上部电线的侧面和底部; 并且上导电衬套与下芯体导体接触并且还与衬套到衬垫接触区域中的下导电衬套接触。

2. 发明申请

US20070033427A1 Power efficient cycle stealing 审中-公开
标题翻译：有效的循环窃取
公开(公告)号：US20070033427A1
公开(公告)日：2007-02-08
申请号：US11184421
申请日：2005-07-19
申请人： Anthony Correale , Benjamin Bowers , Ying Brown , Veena Pureswaran
发明人： Anthony Correale , Benjamin Bowers , Ying Brown , Veena Pureswaran
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/10
摘要： Arrangements and methods to cycle steal and reduce power consumption in an integrated circuit are disclosed. Embodiments of the invention exploit the art of cycle stealing for increased system performance, while facilitating a more power efficient bypass mode when power conservation is desired over performance. One embodiment includes a network of integrated delay elements employing a multiplexor to transfer either a normal or a delayed clock signal to a clock splitter. Another embodiment includes a network of delay elements, configured to enable or disable power conservation. A further embodiment integrates a configurable delay circuit into a clock splitter arrangement.
摘要翻译：公开了在集成电路中循环窃取和降低功耗的安排和方法。本发明的实施例利用循环窃取的技术来提高系统性能，同时在期望功率节省对性能的同时促进更节能的旁路模式。一个实施例包括采用多路复用器将正常或延迟的时钟信号传送到时钟分离器的集成延迟元件的网络。另一实施例包括被配置为启用或禁用功率节省的延迟元件网络。另一实施例将可配置的延迟电路集成到时钟分配器装置中。

3. 发明申请

US20060225005A1 VIA REDUNDANCY BASED ON SUBNET TIMING INFORMATION, TARGET VIA DISTANT ALONG PATH FROM SOURCE AND/OR TARGET VIA NET/SUBNET CHARACTERISTIC 有权
标题翻译：通过基于子网时序信息的通信系统，通过网络/子网特征通过远离源和/或目标的目标
公开(公告)号：US20060225005A1
公开(公告)日：2006-10-05
申请号：US10907496
申请日：2005-04-04
申请人： Anthony Correale , Lewis Dewey , Jason Hibbeler
发明人： Anthony Correale , Lewis Dewey , Jason Hibbeler
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Methods, systems and program products are disclosed that prioritize each target via for via redundancy based on at least one of the following: subnet timing information, a distance of a target via along a path from a driving source and a target via net/subnet characteristic, and attempt to add a redundant via to each target via based on the prioritization. The invention improves overall yield and reduces timing sensitivity to AC-related defects.
摘要翻译：公开了方法，系统和程序产品，其基于以下至少一个来为每个目标优先化经过冗余：子网定时信息，目标通路沿着来自驱动源的路径和目标经由网络/子网特性的距离，并尝试根据优先级将冗余通道添加到每个目标。本发明提高了整体产量并降低了与AC相关缺陷的时序灵敏度。

4. 发明申请

US20060279334A1 SINGLE SUPPLY LEVEL CONVERTER 有权
标题翻译：单电源电平转换器
公开(公告)号：US20060279334A1
公开(公告)日：2006-12-14
申请号：US11466754
申请日：2006-08-23
申请人： Anthony Correale , Rajiv Joshi , David Kung , Zhigang Pan , Ruchir Puri
发明人： Anthony Correale , Rajiv Joshi , David Kung , Zhigang Pan , Ruchir Puri
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K19/0948
摘要： A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.
摘要翻译：用于连接由不同电源电压提供的两个电路的电平转换器，以及包括在两个不同电压岛中的电平转换器接口电路的集成电路。第一缓冲器由虚拟电源提供，并从低电压电路接收输入信号。第一个缓冲器驱动第二个缓冲器，该缓冲器由较高的电源电压供电。来自第二缓冲器的输出切换电源选择以选择性地将较高电源电压或降低的电源电压传递到第一缓冲器。

5. 发明申请

US20050114815A1 Method and program product of level converter optimization 失效
标题翻译：电平转换器优化的方法和程序产品
公开(公告)号：US20050114815A1
公开(公告)日：2005-05-26
申请号：US10720562
申请日：2003-11-24
申请人： Anthony Correale , David Kung , Douglass Lamb , Zhigang Pan , Ruchir Puri
发明人： Anthony Correale , David Kung , Douglass Lamb , Zhigang Pan , Ruchir Puri
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： A method and program product for optimizing level converter placement in a multi supply integrated circuit. Each level converter is placed at a minimum power point to minimize net power and transitional delay from a first (low) voltage net source through the level converter and to a second (higher) voltage net sink. Then, inefficient level converters are eliminated. Level converters with fanin cones below a selected minimum cone size are deleted and low voltage sources to the deleted level converter reverted. Higher voltage level circuit elements receiving inputs from multiple level converters are replaced with equivalent low voltage circuit elements. Low voltage buffer driving level converters are both replaced by a single said level converter.
摘要翻译：一种用于优化多电源集成电路中的电平转换器放置的方法和程序产品。每个电平转换器被放置在最小功率点以最小化净功率和从第一（低）电压净源通过电平转换器到第二（较高）电压净接收器的过渡延迟。然后，消除了低效率的电平转换器。具有低于选定的最小锥度尺寸的扇形锥体的电平转换器被删除，并且删除的电平转换器的低电压源恢复。接收来自多电平转换器的输入的更高电压电平的电路元件被等效的低电压电路元件代替。低电压缓冲器驱动电平转换器都由单个所述电平转换器代替。

6. 发明授权

US4880754A Method for providing engineering changes to LSI PLAs 失效
标题翻译：为LSI PLA提供工程变更的方法
公开(公告)号：US4880754A
公开(公告)日：1989-11-14
申请号：US69915
申请日：1987-07-06
申请人： Anthony Correale
发明人： Anthony Correale
IPC分类号： H03K19/177 , H01L21/768 , H01L21/82 , H01L21/822 , H01L23/525 , H01L27/04
CPC分类号： H01L23/525 , H01L21/76886 , H01L21/76892 , H01L2924/0002 , Y10S148/104 , Y10S148/143
摘要： A method for providing engineering changes to LSI PLAs. One or more additional input lines, output lines, and/or product terms are provided in the overall mask set, however, logically unconnected to the rest of the PLA, which is designed to provide the desired PLA function. The additional lines and terms are provided so as to be able to be connected to the PLA, and provide additional personalization by changes to the contact mask and masks for subsequent process steps to contact. The invention may be incorporated in an existing PLA macro assembler system. By simply redefining certain cells the additional devices may be incorporated through those redefined individual cells. Thus, the invention is relatively easy to retrofit to existing PLA macro assembler systems.

7. 发明申请

US20080115093A1 SYSTEMS AND MEDIA TO IMPROVE MANUFACTURABILITY OF SEMICONDUCTOR DEVICES 有权
标题翻译：系统和介质提高半导体器件的制造能力
公开(公告)号：US20080115093A1
公开(公告)日：2008-05-15
申请号：US11971171
申请日：2008-01-08
申请人： Benjamin Bowers , Anthony Correale
发明人： Benjamin Bowers , Anthony Correale
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/12 , Y02P90/265
摘要： Methods, systems, and media to improve the manufacturability of cells and structures within cells of an integrated circuit are disclosed. Embodiments comprise a method of arranging programmable cells, routing the programmable cells, analyzing the cell arrangement and interconnect wiring for manufacturing improvement opportunities, and modifying the programmable cell structures to incorporate the manufacturing improvements. In some embodiments, wires are spread to prevent shorting. In other embodiments, the reliability of contacts and vias is improved by adding additional metallization to the areas surrounding the contacts and vias, or by adding redundant contacts and vias. In one embodiment, a series of manufacturing improvements are made to integrated circuit cells in an iterative fashion.
摘要翻译：公开了用于提高集成电路单元内的单元和结构的可制造性的方法，系统和介质。实施例包括布置可编程单元，布线可编程单元，分析单元布置并互连布线以用于制造改进机会的方法，以及修改可编程单元结构以结合制造改进。在一些实施例中，布线以防止短路。在其他实施例中，通过向周围的触点和通孔附加额外的金属化，或通过添加冗余的触点和通孔来改善触点和通孔的可靠性。在一个实施例中，以迭代方式对集成电路单元进行一系列制造改进。

8. 发明申请

US20070192752A1 Influence-based circuit design 失效
标题翻译：基于影响的电路设计
公开(公告)号：US20070192752A1
公开(公告)日：2007-08-16
申请号：US11354425
申请日：2006-02-15
申请人： Subhrajit Bhattacharya , Anthony Correale , Nathaniel Hieter , Veena Pureswaran , Ruchir Puri
发明人： Subhrajit Bhattacharya , Anthony Correale , Nathaniel Hieter , Veena Pureswaran , Ruchir Puri
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/08
摘要： An improved solution for designing a circuit is provided. A set of target paths, each of which has a performance attribute that is targeted for improvement, is obtained from a design for the circuit. An influence for one or more of the nodes in the set of target paths is obtained. One or more of the nodes are selected for improvement using the influence. Subsequently, the performance attribute for each selected node is improved. For example, an implementation of the node can be replaced with an implementation having an improved performance attribute. The relative improvement provided by an alternative implementation versus a relative detriment to another performance attribute can be obtained and used in selecting the node(s) for improvement. In one embodiment, the relative improvement and influence are used to obtain a sensitivity metric for each alternative implementation, which is used in selecting the node(s) for improvement. In this manner, the circuit can be improved in a more effective manner.
摘要翻译：提供了一种改进的设计电路解决方案。从电路的设计中获得一组目标路径，每个目标路径具有旨在改进的性能属性。获得对目标路径集中的一个或多个节点的影响。选择一个或多个节点用于使用影响进行改进。随后，提高了每个选定节点的性能属性。例如，可以用具有改进的性能属性的实现来替换节点的实现。可以获得替代实现提供的相对改进与对另一性能属性的相对损害，并用于选择节点以进行改进。在一个实施例中，使用相对改进和影响来获得用于选择节点以进行改进的每个备选实现的灵敏度度量。以这种方式，可以以更有效的方式改善电路。

9. 发明申请

US20070170553A1 Methods and apparatuses for creating integrated circuit capacitance from gate array structures 失效
标题翻译：从门阵列结构产生集成电路电容的方法和装置
公开(公告)号：US20070170553A1
公开(公告)日：2007-07-26
申请号：US11337010
申请日：2006-01-20
申请人： Anthony Correale , Benjamin Bowers , Douglass Lamb , Nishith Rohatgi
发明人： Anthony Correale , Benjamin Bowers , Douglass Lamb , Nishith Rohatgi
IPC分类号： H01L23/62
CPC分类号： H01L27/11807 , H01L27/0207 , H01L27/11898 , H01L28/40
摘要： Methods and apparatuses for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise a method of placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.
摘要翻译：公开了在集成电路中使用门阵列来形成电容结构的方法和装置。实施例包括将P型场效应晶体管（P-fets）和N型场效应晶体管（N-fets）的栅极阵列放置在集成电路设计中的方法，将一个或多个P-fets的漏极和源极以及用于一个或多个N-fets的门到电源地，以及将一个或多个P-fets的栅极和用于一个或多个N-fets的漏极和源耦合到电源的正电压。在一些实施例中，通过将一个或多个P-fets和一个或多个N-fets分别偏置到正电压和地电位，P-fets和N-fets的电容式设备的源极到漏极泄漏电流被最小化。在其他实施例中，可以使用可熔元件实现电容结构，以在短路的情况下隔离电容结构。

10. 发明申请

US20050110519A1 Single supply level converter 有权
标题翻译：单电源电平转换器
公开(公告)号：US20050110519A1
公开(公告)日：2005-05-26
申请号：US10720466
申请日：2003-11-24
申请人： Anthony Correale , Rajiv Joshi , David Kung , Zhigang Pan , Ruchir Puri
发明人： Anthony Correale , Rajiv Joshi , David Kung , Zhigang Pan , Ruchir Puri
IPC分类号： H03K19/0185 , H03K19/0948 , H03K19/094
CPC分类号： H03K19/018521 , H03K19/0948
摘要： A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.
摘要翻译：用于连接由不同电源电压提供的两个电路的电平转换器，以及包括在两个不同电压岛中的电平转换器接口电路的集成电路。第一缓冲器由虚拟电源提供，并从低电压电路接收输入信号。第一个缓冲器驱动第二个缓冲器，该缓冲器由较高的电源电压供电。来自第二缓冲器的输出切换电源选择以选择性地将较高电源电压或降低的电源电压传递到第一缓冲器。

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