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1. 发明授权

US07915667B2 Integrated circuits having a contact region and methods for manufacturing the same 有权
标题翻译：具有接触区域的集成电路及其制造方法
公开(公告)号：US07915667B2
公开(公告)日：2011-03-29
申请号：US12137388
申请日：2008-06-11
申请人： Roman Knoefler , Michael Specht , Franz Hofmann , Florian Beug , Dirk Manger , Stephan Riedel
发明人： Roman Knoefler , Michael Specht , Franz Hofmann , Florian Beug , Dirk Manger , Stephan Riedel
IPC分类号： H01L29/792 , H01L29/788 , H01L21/336
CPC分类号： H01L21/28282 , H01L21/28273 , H01L21/8221 , H01L27/11565 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/792 , H01L29/7926
摘要： In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.
摘要翻译：在一个实施例中，提供了具有存储单元布置的集成电路。存储单元布置可以包括基板，设置在基板上方的散热片结构和存储单元接触区域。鳍结构可以包括具有多个存储单元结构的存储单元区域，每个存储单元结构具有相应存储单元的有源区域。此外，存储器单元接触区域可以被配置为电接触每个存储单元结构，其中存储单元接触区域可以包括多个接触区域，这些接触区域在平行于存储器单元结构的方向上相对于彼此至少部分地位移基材的主要加工表面。

2. 发明申请

US20090309152A1 Integrated Circuits Having a Contact Region and Methods for Manufacturing the Same 有权
标题翻译：具有接触区域的集成电路及其制造方法
公开(公告)号：US20090309152A1
公开(公告)日：2009-12-17
申请号：US12137388
申请日：2008-06-11
申请人： Roman Knoefler , Michael Specht , Franz Hofmann , Florian Beug , Dirk Manger , Stephan Riedel
发明人： Roman Knoefler , Michael Specht , Franz Hofmann , Florian Beug , Dirk Manger , Stephan Riedel
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , H01L21/28273 , H01L21/8221 , H01L27/11565 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/792 , H01L29/7926
摘要： In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.
摘要翻译：在一个实施例中，提供了具有存储单元布置的集成电路。存储单元布置可以包括基板，设置在基板上方的散热片结构和存储单元接触区域。鳍结构可以包括具有多个存储单元结构的存储单元区域，每个存储单元结构具有相应存储单元的有源区域。此外，存储器单元接触区域可以被配置为电接触每个存储单元结构，其中存储单元接触区域可以包括多个接触区域，这些接触区域在平行于存储器单元结构的方向上相对于彼此至少部分地位移基材的主要加工表面。

3. 发明申请

US20070075381A1 Semiconductor memory device and method of production 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070075381A1
公开(公告)日：2007-04-05
申请号：US11241878
申请日：2005-09-30
申请人： Stefano Parascandola , Roman Knoefler , Stephan Riedel , Dominik Olligs , Torsten Mueller , Dirk Caspary
发明人： Stefano Parascandola , Roman Knoefler , Stephan Riedel , Dominik Olligs , Torsten Mueller , Dirk Caspary
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11565 , H01L27/11568
摘要： The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.
摘要翻译：位线通过牺牲性硬掩模层的掺杂剂的注入而产生，牺牲性硬掩模层随后由存储单元阵列中由多晶硅形成的栅电极代替。横向于位线运行的存储单元阵列的条纹区域由阻塞层保留以被位线触点占据。在这些区域中，硬掩模用于形成与植入的掩埋位线自对准的接触孔。在阻塞区域之间，字线正常布置在位线上。

4. 发明授权

US07642158B2 Semiconductor memory device and method of production 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07642158B2
公开(公告)日：2010-01-05
申请号：US11241878
申请日：2005-09-30
申请人： Stefano Parascandola , Roman Knoefler , Stephan Riedel , Dominik Olligs , Torsten Mueller , Dirk Caspary
发明人： Stefano Parascandola , Roman Knoefler , Stephan Riedel , Dominik Olligs , Torsten Mueller , Dirk Caspary
IPC分类号： H01L21/336 , H01L29/94
CPC分类号： H01L27/115 , H01L27/11565 , H01L27/11568
摘要： The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.
摘要翻译：位线通过牺牲性硬掩模层的掺杂剂的注入而产生，牺牲性硬掩模层随后由存储单元阵列中由多晶硅形成的栅电极代替。横向于位线运行的存储单元阵列的条纹区域由阻塞层保留以被位线触点占据。在这些区域中，硬掩模用于形成与植入的掩埋位线自对准的接触孔。在阻塞区域之间，字线正常布置在位线上。

5. 发明授权

US07026220B1 Method for production of charge-trapping memory devices 失效
标题翻译：电荷俘获存储器件的制造方法
公开(公告)号：US07026220B1
公开(公告)日：2006-04-11
申请号：US11006484
申请日：2004-12-07
申请人： Georg Tempel , Elard Stein von Kamienski , Stephan Riedel , Veronika Polei , Roland Haberkern , Roman Knoefler
发明人： Georg Tempel , Elard Stein von Kamienski , Stephan Riedel , Veronika Polei , Roland Haberkern , Roman Knoefler
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L27/11568 , H01L27/115 , Y10S438/954
摘要： The method aims at improving the charge confinement of the memory layer at the edges facing the regions of buried bitlines. After the deposition of the memory layer between confinement layers and the implantation of dopants for bitlines and source/drain regions, an oxidation of semiconductor material to form upper bitline isolation regions takes place. By this method, additional oxide regions are produced at the edges of the memory layer in the same oxidation step. Either a silicon layer may be deposited and reduced to sidewall spacers, which are subsequently oxidized; or recesses are etched into the memory layer and subsequently filled with semiconductor oxide.
摘要翻译：该方法旨在改善面向掩埋位线区域的边缘处的存储层的电荷限制。在限制层之间的存储层沉积和用于位线和源/漏区的掺杂剂的注入之后，发生半导体材料的氧化以形成上位线隔离区。通过该方法，在相同的氧化步骤中在存储层的边缘产生附加的氧化物区域。可以将硅层沉积并还原成侧壁间隔物，其随后被氧化; 或凹槽蚀刻到存储层中，随后填充半导体氧化物。

6. 发明授权

US07427548B2 Method for producing charge-trapping memory cell arrays 有权
标题翻译：电荷俘获存储单元阵列的制造方法
公开(公告)号：US07427548B2
公开(公告)日：2008-09-23
申请号：US11170187
申请日：2005-06-29
申请人： Stephan Riedel , Stefano Parascandola
发明人： Stephan Riedel , Stefano Parascandola
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L29/66833
摘要： A memory layer sequence comprising a lower confinement layer (2), a charge-trapping layer (3), and an upper confinement layer (4) is applied on the main surface of a silicon substrate (1). By a photolithography step, trenches running parallel at a distance from one another are etched to delimitate the active area. A trench filling (7) is applied by growth or deposition of dielectric material or by a selective oxidation of the substrate material. After the removal of the charge-trapping layer sequence in a peripheral area and the deposition of a gate dielectric material provided for the transistors of an addressing circuitry, wordline stacks (8) are formed.
摘要翻译：在硅衬底（1）的主表面上施加包括下约束层（2），电荷俘获层（3）和上限制层（4）的存储层序列。通过光刻步骤，蚀刻彼此间隔一定距离的平行沟槽，以界定有效面积。沟槽填充（7）通过介电材料的生长或沉积或通过基底材料的选择性氧化来施加。在去除外围区域中的电荷捕获层序列并且为寻址电路的晶体管提供的栅极电介质材料的沉积形成字线叠层（8）之后。

7. 发明授权

US07288812B2 Semiconductor memory with virtual ground architecture 有权
标题翻译：具有虚拟地面架构的半导体存储器
公开(公告)号：US07288812B2
公开(公告)日：2007-10-30
申请号：US10857637
申请日：2004-05-27
申请人： Stephan Riedel
发明人： Stephan Riedel
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , G11C16/0491 , H01L27/115
摘要： Insulation regions in the manner of STI isolations, which run transversely with respect to the word lines, isolate the source/drain regions of adjacent memory cells. Metallic bit lines are applied on the top side and patterned for example along zigzag lines such that the source/drain regions of a memory transistor which are contact-connected by the bit lines are in each case electrically connected by two mutually adjacent bit lines.
摘要翻译：绝缘区域以相对于字线横向延伸的STI隔离的方式隔离相邻存储器单元的源极/漏极区域。金属位线施加在顶侧，并且例如沿着之字形线图案化，使得通过位线接触连接的存储晶体管的源极/漏极区域在每种情况下都由两个相互相邻的位线电连接。

8. 发明申请

US20060114724A1 Non-volatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20060114724A1
公开(公告)日：2006-06-01
申请号：US11000335
申请日：2004-11-30
申请人： Stephan Riedel , Elard Kamienski , Norbert Schulze
发明人： Stephan Riedel , Elard Kamienski , Norbert Schulze
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： H01L27/115 , G11C16/0466 , H01L27/1203
摘要： A non-volatile semiconductor memory includes a substrate having a substrate region, at least one word line, a plurality of non-volatile memory cells arranged in a plurality of sectors and further comprising first wells of a first doping type, electrically insulating elements and switching elements. Each sector comprises a plurality of non-volatile memory cells commonly arranged in a respective first well. The at least one word line electrically connecting memory cells of a group of sectors among the plurality of sectors. The first wells are separated from the substrate region and from each other by means of the electrically insulating elements. Each first well is connected to a respective switching element and the semiconductor memory is constructed such that each first well is biasable to a predetermined potential by means of the respective switching element. Further, a method is provided for operating the above non-volatile semiconductor memory.
摘要翻译：非挥发性半导体存储器包括具有衬底区域，至少一个字线，布置在多个扇区中的多个非易失性存储单元的衬底，并且还包括第一掺杂类型的第一阱，电绝缘元件和开关元素。每个扇区包括通常布置在相应的第一阱中的多个非易失性存储单元。所述至少一个字线电连接所述多个扇区中的一组扇区的存储单元。第一个阱通过电绝缘元件从衬底区域和彼此分离。每个第一阱连接到相应的开关元件，并且半导体存储器被构造成使得每个第一阱通过相应的开关元件可偏置到预定电位。此外，提供了用于操作上述非易失性半导体存储器的方法。

9. 发明授权

US09039003B2 Method of, and apparatus for, processing sheets of different formats 有权
标题翻译：处理不同格式的纸张的方法和装置
公开(公告)号：US09039003B2
公开(公告)日：2015-05-26
申请号：US14199252
申请日：2014-03-06
申请人： Toni Egli , Stephan Riedel
发明人： Toni Egli , Stephan Riedel
IPC分类号： B41F13/64 , B65H29/51 , B65H39/02 , B65H39/105 , B65H39/00
CPC分类号： B41F13/64 , B65H29/51 , B65H39/00 , B65H39/02 , B65H39/105 , B65H2301/141 , B65H2301/22 , B65H2301/4213 , B65H2301/4312 , B65H2404/42 , B65H2404/652 , B65H2405/541 , B65H2511/11 , B65H2513/42 , B65H2701/1131 , B65H2220/01 , B65H2220/02
摘要： An apparatus for processing sheets of different formats, the apparatus including a feeding device that feed sheets of different formats in a feeding direction one behind the other, and at a certain conveying speed, at least two collecting drums disposed downstream of the feeding device, the at least two collecting drums having cylindrical lateral surfaces that rotate about an axis of rotation, securing means for temporarily securing the fed sheets on a circumference of the at least two collecting drums, a drive device that drives the collecting drums in rotation at a circumferential speed that corresponds to the conveying speed of the feeding device, and a sensing device for sensing the sheets of different formats moving past is arranged along the conveying path and senses the leading edge of the sheets of different formats, as seen in the feeding direction, or markings applied to the sheets of different formats.
摘要翻译：一种用于处理不同格式的片材的装置，该装置包括一个馈送装置，该馈送装置沿一个接一个的馈送方向以一定的传送速度馈送不同格式的片材，至少两个设置在馈送装置下游的收集鼓，至少两个收集鼓，其具有围绕旋转轴线旋转的圆柱形侧表面;用于将进给的片材临时固定在至少两个收集鼓的圆周上的固定装置，驱动装置，其以圆周速度旋转收集鼓对应于进给装置的传送速度，以及用于感测移动过去的不同格式的纸张的感测装置沿着传送路径布置，并且感测从进给方向看不同格式的纸张的前缘，或者标记应用于不同格式的纸张。

10. 发明授权

US08708326B2 Method of, and apparatus for, processing sheets of different formats 有权
标题翻译：处理不同格式的纸张的方法和装置
公开(公告)号：US08708326B2
公开(公告)日：2014-04-29
申请号：US13427154
申请日：2012-03-22
申请人： Toni Egli , Stephan Riedel
发明人： Toni Egli , Stephan Riedel
IPC分类号： B41F13/64
CPC分类号： B41F13/64 , B65H29/51 , B65H39/00 , B65H39/02 , B65H39/105 , B65H2301/141 , B65H2301/22 , B65H2301/4213 , B65H2301/4312 , B65H2404/42 , B65H2404/652 , B65H2405/541 , B65H2511/11 , B65H2513/42 , B65H2701/1131 , B65H2220/01 , B65H2220/02
摘要： Sheets of different formats, i.e. of different format lengths, are transported in a feeding direction one behind the other; and at a certain conveying speed, to at least two collecting drums, which have essentially cylindrical lateral surfaces. Each of these collecting drums is driven about an axis of rotation at a circumferential speed, which corresponds essentially to the feeding speed of the sheets. The first incoming sheet is secured temporarily on one of the collecting drums, while the following, second sheet is secured temporarily on the other collecting drum. At a suitable point in time, the two sheets secured on the collecting drums are detached from the collecting drums and brought together with the third fed sheet to form a sub-product or end product.
摘要翻译：不同格式，即不同格式长度的纸张沿进给方向一个接一个地传送; 并以一定的输送速度传送到至少两个具有基本上圆柱形侧表面的收集鼓。这些收集鼓中的每一个围绕旋转轴以圆周速度驱动，其基本上对应于片材的进给速度。第一进纸片被临时固定在一个收集鼓上，而下面的第二纸张暂时固定在另一个收集鼓上。在合适的时间点，固定在收集鼓上的两个片材与收集鼓分离，并与第三个送入的片材一起形成副产品或最终产品。

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