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    • 1. 发明授权
    • Monolithic planar doped barrier limiter
    • 单片平面掺杂势垒限制器
    • US4654609A
    • 1987-03-31
    • US705267
    • 1985-02-25
    • Samuel Dixon, Jr.Thomas R. AuCoinRoger J. Malik
    • Samuel Dixon, Jr.Thomas R. AuCoinRoger J. Malik
    • H01L29/36H01L29/861H03G11/02H01P1/22
    • H03G11/025H01L29/365H01L29/8618
    • A passive millimeter wave image guide power limiter comprising a length ofielectric transmission line or waveguide for millimeter wave frequencies located on a relatively thin conductive ground plane forming thereby an image guide and including a planar doped barrier diode structure formed in the dielectric transmission line with the planar doped barrier structure being integrally grown in a slot milled in the constituent material, i.e. gallium arsenide, of the waveguide transversely across the width dimension thereof so as to be oriented perpendicular to the flow of RF power being propagated along its length dimension. The planar doped barrier structure becomes conductive at a predetermined power level to reflect any further incident RF power back toward the power source.
    • 一种无源毫米波图像引导功率限制器,其包括位于相对薄的导电接地平面上的毫米波频率的介电传输线或波导的长度,从而形成图像引导件,并且包括形成在电介质传输线中的平面掺杂阻挡二极管结构, 平面掺杂阻挡结构整体生长在波导管的构成材料(即砷化镓)中铣削的槽中,横向穿过其宽度尺寸,以便垂直于沿着其长度尺寸传播的RF功率的流动。 平面掺杂阻挡结构以预定的功率电平变为导通,以将进一步的入射RF功率反射回电源。
    • 2. 发明授权
    • Planar doped barrier gate field effect transistor
    • 平面掺杂栅极场效应晶体管
    • US4442445A
    • 1984-04-10
    • US323858
    • 1981-11-23
    • Roger J. MalikThomas R. AuCoin
    • Roger J. MalikThomas R. AuCoin
    • H01L29/10H01L29/80H01L27/12H01L29/12
    • H01L29/80H01L29/10
    • Disclosed is an epitaxial layer field effect transistor having a planar dd barrier gate formed on an n-type semiconductor planar channel region between drain and source terminals formed on the surface of the channel region. The semiconductor channel region is fabricated on a semiconductor substrate, preferably GaAs and being separated therefrom by one or more semiconductor planar buffer regions. The planar doped barrier gate comprises an n.sup.+ -.pi.-p.sup.+ -.pi. structure grown by molecular beam epitaxy over the n-type channel region. Application of an electrical potential to the gate modulates the channel charge depletion in the semiconductor channel region underlying the gate causing a variation in the channel conductance laterally between the source and drain terminals.
    • 公开了一种外延层场效应晶体管,其具有形成在沟道区域表面上形成的漏极和源极端子之间的n型半导体平面沟道区上的平面掺杂势垒栅。 半导体沟道区域制造在半导体衬底上,优选地是GaAs,并由一个或多个半导体平面缓冲区与其分离。 平面掺杂阻挡栅极包括通过n型沟道区域上的分子束外延生长的n + -pi-p +-π结构。 向栅极施加电势调制栅极下方的半导体沟道区域中的沟道电荷耗尽,导致源极和漏极端子之间的沟道电导的横向变化。