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1. 发明授权

US5765219A Apparatus and method for incrementally accessing a system memory 失效
标题翻译：用于递增访问系统存储器的装置和方法
公开(公告)号：US5765219A
公开(公告)日：1998-06-09
申请号：US598539
申请日：1996-02-08
申请人： Rodney Hugh Densham , Christopher Michael McCulloch , Peter Charles Eastty
发明人： Rodney Hugh Densham , Christopher Michael McCulloch , Peter Charles Eastty
IPC分类号： G11C8/04 , G06F13/00
CPC分类号： G11C8/04
摘要： Data storage apparatus comprises: a memory having a plurality of addressable memory locations for storage of data items and memory address input means for receiving addresses of locations to be accessed; main input means for receiving an input address corresponding to a memory location; a counter for changing a count in response to a clock signal; address adjustment means for combining the count with an input address to generate an adjusted address corresponding to a memory location and supplying the adjusted address to the memory address input means; and means for accessing the memory location at the address supplied to the memory address input means. Also provided is a data storage method, and data processing systems including the data storage systems.
摘要翻译：数据存储装置包括：存储器，具有用于存储数据项的多个可寻址存储器位置和用于接收要访问的位置的地址的存储器地址输入装置; 主输入装置，用于接收对应于存储器位置的输入地址; 用于响应于时钟信号改变计数的计数器; 地址调整装置，用于将计数与输入地址组合以产生对应于存储器位置的调整地址，并将调整后的地址提供给存储器地址输入装置; 以及用于在提供给存储器地址输入装置的地址处访问存储器位置的装置。还提供了数据存储方法，以及包括数据存储系统的数据处理系统。

2. 发明授权

US5898878A Data processing system having capability to interpolate processing coefficients 失效
标题翻译：数据处理系统具有内插处理系数的能力
公开(公告)号：US5898878A
公开(公告)日：1999-04-27
申请号：US48133
申请日：1998-03-25
申请人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
发明人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
IPC分类号： G06F15/16 , G06F9/48 , G06F11/10 , G06F11/30 , G06F11/32 , G06F15/177 , G06F17/17 , G06F7/00 , G06F9/46
CPC分类号： G06F11/3072 , G06F11/10 , G06F17/17 , G06F11/327 , G06F2201/86 , G06F2201/88
摘要： A method and apparatus is provided for generating an interrupt signal in a data processing system, the interrupt signal being supplied to a control processor of the system to indicate the occurrence of any of a plurality of predetermined events in the system. The method and apparatus operate by: writing data to at least one memory location of a plurality of pairs of memory locations A,B of the system in dependence upon the event to be indicated, the pairs of memory locations A,B being predefined in the system for respective ones of the events; reading data from the pairs of memory locations A,B; processing the data read from each pair of memory locations A,B to generate interrupt data indicative of whether the associated event has occurred, and if so transmitting an interrupt signal to the control processor; and writing the interrupt data corresponding to the events to respective third memory locations C, the third memory locations C being predefined in the control processor for the events. On receipt of an interrupt signal, the control processor reads the interrupt data in the third memory locations C to determine the event indicated by the interrupt signal.
摘要翻译：提供了一种用于在数据处理系统中产生中断信号的方法和装置，所述中断信号被提供给系统的控制处理器，以指示系统中多个预定事件中的任何一个发生。该方法和装置通过以下方式操作：根据要指示的事件将数据写入系统的多对存储器位置A，B的至少一个存储器位置，存储器位置A，B在系统为各自的事件; 从存储单元对A，B中读取数据; 处理从每对存储器位置A，B读取的数据，以产生指示相关联的事件是否已经发生的中断数据，并且如果发送中断信号到控制处理器; 并将与事件相对应的中断数据写入相应的第三存储器位置C，在控制处理器中为事件预定义第三存储单元C. 在接收到中断信号时，控制处理器读取第三存储器位置C中的中断数据，以确定由中断信号指示的事件。

3. 发明授权

US5740449A Method and apparatus for managing interrupts in a data processing system 失效
标题翻译：用于管理数据处理系统中的中断的方法和装置
公开(公告)号：US5740449A
公开(公告)日：1998-04-14
申请号：US598537
申请日：1996-02-08
申请人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
发明人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
IPC分类号： G06F15/16 , G06F9/48 , G06F11/10 , G06F11/30 , G06F11/32 , G06F15/177 , G06F17/17 , G06F9/46 , G06F11/00
CPC分类号： G06F11/3072 , G06F11/10 , G06F17/17 , G06F11/327 , G06F2201/86 , G06F2201/88
摘要： A method and apparatus is provided for generating an interrupt signal in a data processing system, the interrupt signal being supplied to a control processor of the system to indicate the occurrence of any of a plurality of predetermined events in the system. The method and apparatus operate by: writing data to at least one memory location of a plurality of pairs of memory locations A, B of the system in dependence upon the event to be indicated, the pairs of memory locations A, B being predefined in the system for respective ones of the events; reading data from the pairs of memory locations A, B; processing the data read from each pair of memory locations A, B to generate interrupt data indicative of whether the associated event has occurred, and if so transmitting an interrupt signal to the control processor; and writing the interrupt data corresponding to the events to respective third memory locations C, the third memory locations C being predefined in the control processor. On receipt of an interrupt signal, the control processor reads the interrupt data in the third memory locations C to determine the event indicated by the interrupt signal.
摘要翻译：提供了一种用于在数据处理系统中产生中断信号的方法和装置，所述中断信号被提供给系统的控制处理器，以指示系统中多个预定事件中的任何一个发生。该方法和装置通过以下方式操作：根据要指示的事件将数据写入系统的多对存储器位置A，B的至少一个存储器位置，存储器位置A，B在系统为各自的事件; 从存储单元对A，B中读取数据; 处理从每对存储器位置A，B读取的数据，以产生指示相关联的事件是否已经发生的中断数据，并且如果发送中断信号到控制处理器; 并将对应于事件的中断数据写入相应的第三存储器位置C，在控制处理器中预定义第三存储单元C. 在接收到中断信号时，控制处理器读取第三存储器位置C中的中断数据，以确定由中断信号指示的事件。

4. 发明授权

US5881077A Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：US5881077A
公开(公告)日：1999-03-09
申请号：US845559
申请日：1997-04-24
申请人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
发明人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
IPC分类号： G06F15/16 , G06F9/48 , G06F11/10 , G06F11/30 , G06F11/32 , G06F15/177 , G06F17/17 , G06F11/00
CPC分类号： G06F11/3072 , G06F11/10 , G06F17/17 , G06F11/327 , G06F2201/86 , G06F2201/88
摘要： A method and apparatus is provided for generating an interrupt signal in a data processing system, the interrupt signal being supplied to a control processor of the system to indicate the occurrence of any of a plurality of predetermined events in the system. The method and apparatus operate by: writing data to at least one memory location of a plurality of pairs of memory locations A,B of the system in dependence upon the event to be indicated, the pairs of memory locations A,B being predefined in the system for respective ones of the events; reading data from the pairs of memory locations A,B; processing the data read from each pair of memory locations A,B to generate interrupt data indicative of whether the associated event has occurred, and if so transmitting an interrupt signal to the control processor; and writing the interrupt data corresponding to the events to respective third memory locations C, the third memory locations C being predefined in the control processor for the said events. On receipt of an interrupt signal, the control processor reads the interrupt data in the third memory locations C to determine the event indicated by the interrupt signal.
摘要翻译：提供了一种用于在数据处理系统中产生中断信号的方法和装置，所述中断信号被提供给系统的控制处理器，以指示系统中多个预定事件中的任何一个发生。该方法和装置通过以下方式操作：根据要指示的事件将数据写入系统的多对存储器位置A，B的至少一个存储器位置，存储器位置A，B在系统为各自的事件; 从存储单元对A，B中读取数据; 处理从每对存储器位置A，B读取的数据，以产生指示相关联的事件是否已经发生的中断数据，并且如果发送中断信号到控制处理器; 并将对应于事件的中断数据写入相应的第三存储器位置C，在控制处理器中为所述事件预定义第三存储单元C. 在接收到中断信号时，控制处理器读取第三存储器位置C中的中断数据，以确定由中断信号指示的事件。

5. 发明授权

US5802385A Array processing system with each processor including router and which selectively delays input/output of individual processors in response delay instructions 失效
标题翻译：阵列处理系统，每个处理器包括路由器，并且在响应延迟指令中选择性地延迟单个处理器的输入/输出
公开(公告)号：US5802385A
公开(公告)日：1998-09-01
申请号：US515837
申请日：1995-08-16
申请人： Rodney Hugh Densham , Peter Charles Eastty , Conrad Charles Cooke
发明人： Rodney Hugh Densham , Peter Charles Eastty , Conrad Charles Cooke
IPC分类号： G06F15/16 , G06F15/177 , G06F15/80 , H04H60/04 , G06F15/82
CPC分类号： H04H60/04
摘要： In one aspect, the invention provides parallel processing apparatus comprising an array of data processors 4. arranged to operate synchronously, and a plurality of data buses. Each data processor 4 has first and second I/O means 16H, 16V for transfer of data between the processor 4 and respective data buses H,V a plurality of processors 4 being connected to each of the data buses H,V and each processor 4 being connected, via said I/O means 16H, 16V, to a different pair of data buses H,V. Each processor 4 includes selectively operable routing means 32H, 32V for interconnecting the first and second I/O means 16H, 16V to transfer data between the buses H,V connected thereto.
摘要翻译：一方面，本发明提供并行处理装置，其包括布置成同步操作的数据处理器阵列4和多个数据总线。每个数据处理器4具有用于在处理器4和相应的数据总线H，V之间传送数据的第一和第二I / O装置16H，16V，多个处理器4连接到每个数据总线H，V和每个处理器4 通过所述I / O装置16H，16V连接到不同的一对数据总线H，V。每个处理器4包括用于互连第一和第二I / O装置16H，16V的选择性可操作的路由装置32H，32V，以在连接到其之间的总线H，V之间传送数据。

6. 发明授权

US07904301B2 Processing digital data 失效
标题翻译：处理数字数据
公开(公告)号：US07904301B2
公开(公告)日：2011-03-08
申请号：US10526573
申请日：2003-08-08
申请人： Rodney Hugh Densham , William Edmund Cranstoun Kentish , Nicholas John Haynes , Peter Charles Eastty
发明人： Rodney Hugh Densham , William Edmund Cranstoun Kentish , Nicholas John Haynes , Peter Charles Eastty
IPC分类号： G10L19/00
CPC分类号： G11B20/00826 , G11B20/00007 , G11B20/00086 , G11B20/10527
摘要： An original digital audio signal represents unimpaired audio information. The digital audio signal is compressed and encrypted without substantial impairment to produce a first audio signal. A second, unencrypted, audio signal is produced. The first and second audio signals are combined. Preferably the first audio signal is losslessy compressed. The second audio signal may be an impaired version of the original digital audio signal.
摘要翻译：原始数字音频信号表示未受损的音频信息。数字音频信号被压缩和加密而没有实质的损害以产生第一音频信号。产生第二个未加密的音频信号。第一和第二音频信号被组合。优选地，第一音频信号是无损压缩的。第二音频信号可能是原始数字音频信号的受损版本。

7. 发明授权

US06327631B1 Signal processing apparatus 失效
标题翻译：信号处理装置
公开(公告)号：US06327631B1
公开(公告)日：2001-12-04
申请号：US08654217
申请日：1996-05-28
申请人： Peter Charles Eastty , William Edmund Cranstoun Kentish , Christopher Michael McCulloch
发明人： Peter Charles Eastty , William Edmund Cranstoun Kentish , Christopher Michael McCulloch
IPC分类号： G06F104
CPC分类号： H04H60/04
摘要： A processing apparatus includes a network of interconnected processors comprising a plurality of signal processors for digitally processing input signals in real time to generate output signals and one or more control processors, each control processor controlling the operation of a plurality of signal processors. The processing apparatus automatically schedules control tasks in a plurality of time slices, where more than one control processor is provided for coordination between control processors, a wired-OR configuration connection can be provided to synchronise the beginning and/or end of the time slices. A control processor can change an address field of microcode instructions of a signal processor for implementing a multiplexer function. A control delay list can be provided for scheduling control task delays. Control tasks can be allocated to more than one control processor, each control processor then communicating to the other control processors if it completes the task so that the other control processors may abandon further processing of the task. The invention finds particular application to an audio mixing console.
摘要翻译：处理装置包括互连处理器的网络，其包括多个用于实时数字处理输入信号的信号处理器以产生输出信号和一个或多个控制处理器，每个控制处理器控制多个信号处理器的操作。处理装置在多个时间片段中自动调度控制任务，其中提供多于一个控制处理器用于控制处理器之间的协调，可以提供有线配置连接以同步时间片段的开始和/或结束。控制处理器可以改变用于实现复用器功能的信号处理器的微码指令的地址字段。可以提供控制延迟列表用于调度控制任务延迟。控制任务可以被分配给多个控制处理器，然后每个控制处理器如果完成任务则与其他控制处理器进行通信，以便其他控制处理器可以放弃任务的进一步处理。本发明特别适用于音频混合控制台。

8. 发明授权

US5944814A Parallel processing digital audio processing apparatus 失效
标题翻译：并行处理数字音频处理装置
公开(公告)号：US5944814A
公开(公告)日：1999-08-31
申请号：US611081
申请日：1996-03-05
申请人： Christopher Michael McCulloch , Peter Charles Eastty , William Edmund Cranstoun Kentish
发明人： Christopher Michael McCulloch , Peter Charles Eastty , William Edmund Cranstoun Kentish
IPC分类号： H03G3/02 , G06F9/50 , G06F15/80 , H03H17/00 , H03H17/02 , H04H60/04 , G06F15/16
CPC分类号： H04H60/04 , G06F9/5066
摘要： This invention relates to the allocation of object code in multi-processor systems. In particular, techniques are disclosed for efficiently allocating signal processing instructions to a large array of parallel signal processing units.
摘要翻译：本发明涉及多处理器系统中目标代码的分配。特别地，公开了用于将信号处理指令有效地分配给大量并行信号处理单元阵列的技术。

9. 发明授权

US6044223A Object code allocation in multiple systems 失效
标题翻译：多个系统中的对象代码分配
公开(公告)号：US6044223A
公开(公告)日：2000-03-28
申请号：US108103
申请日：1998-06-30
申请人： Christopher Michael McCulloch , Peter Charles Eastty , William Edmund Cranstoun Kentish
发明人： Christopher Michael McCulloch , Peter Charles Eastty , William Edmund Cranstoun Kentish
IPC分类号： H03G3/02 , G06F9/50 , G06F15/80 , H03H17/00 , H03H17/02 , H04H60/04 , G06F9/45
CPC分类号： H04H60/04 , G06F9/5066
摘要： This invention relates to the allocation of object code in multi-processor systems. In particular, techniques are disclosed for efficiently allocating signal processing instructions to a large array of parallel signal processing units.
摘要翻译：本发明涉及多处理器系统中对象代码的分配。特别地，公开了用于将信号处理指令有效地分配给大量并行信号处理单元阵列的技术。

10. 发明授权

US5964865A Object code allocation in multiple processor systems 失效
标题翻译：多处理器系统中的对象代码分配
公开(公告)号：US5964865A
公开(公告)日：1999-10-12
申请号：US107862
申请日：1998-06-30
申请人： Christopher Michael McCulloch , Peter Charles Eastty , William Edmund Cranstoun Kentish
发明人： Christopher Michael McCulloch , Peter Charles Eastty , William Edmund Cranstoun Kentish
IPC分类号： H03G3/02 , G06F9/50 , G06F15/80 , H03H17/00 , H03H17/02 , H04H60/04
CPC分类号： H04H60/04 , G06F9/5066
摘要： This invention relates to the allocation of object code in multi-processor systems. In particular, techniques are disclosed for efficiently allocating signal processing instructions to a large array of parallel signal processing units.
摘要翻译：本发明涉及多处理器系统中目标代码的分配。特别地，公开了用于将信号处理指令有效地分配给大量并行信号处理单元阵列的技术。

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