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1. 发明授权

US5740449A Method and apparatus for managing interrupts in a data processing system 失效
标题翻译：用于管理数据处理系统中的中断的方法和装置
公开(公告)号：US5740449A
公开(公告)日：1998-04-14
申请号：US598537
申请日：1996-02-08
申请人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
发明人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
IPC分类号： G06F15/16 , G06F9/48 , G06F11/10 , G06F11/30 , G06F11/32 , G06F15/177 , G06F17/17 , G06F9/46 , G06F11/00
CPC分类号： G06F11/3072 , G06F11/10 , G06F17/17 , G06F11/327 , G06F2201/86 , G06F2201/88
摘要： A method and apparatus is provided for generating an interrupt signal in a data processing system, the interrupt signal being supplied to a control processor of the system to indicate the occurrence of any of a plurality of predetermined events in the system. The method and apparatus operate by: writing data to at least one memory location of a plurality of pairs of memory locations A, B of the system in dependence upon the event to be indicated, the pairs of memory locations A, B being predefined in the system for respective ones of the events; reading data from the pairs of memory locations A, B; processing the data read from each pair of memory locations A, B to generate interrupt data indicative of whether the associated event has occurred, and if so transmitting an interrupt signal to the control processor; and writing the interrupt data corresponding to the events to respective third memory locations C, the third memory locations C being predefined in the control processor. On receipt of an interrupt signal, the control processor reads the interrupt data in the third memory locations C to determine the event indicated by the interrupt signal.
摘要翻译：提供了一种用于在数据处理系统中产生中断信号的方法和装置，所述中断信号被提供给系统的控制处理器，以指示系统中多个预定事件中的任何一个发生。该方法和装置通过以下方式操作：根据要指示的事件将数据写入系统的多对存储器位置A，B的至少一个存储器位置，存储器位置A，B在系统为各自的事件; 从存储单元对A，B中读取数据; 处理从每对存储器位置A，B读取的数据，以产生指示相关联的事件是否已经发生的中断数据，并且如果发送中断信号到控制处理器; 并将对应于事件的中断数据写入相应的第三存储器位置C，在控制处理器中预定义第三存储单元C. 在接收到中断信号时，控制处理器读取第三存储器位置C中的中断数据，以确定由中断信号指示的事件。

2. 发明授权

US5898878A Data processing system having capability to interpolate processing coefficients 失效
标题翻译：数据处理系统具有内插处理系数的能力
公开(公告)号：US5898878A
公开(公告)日：1999-04-27
申请号：US48133
申请日：1998-03-25
申请人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
发明人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
IPC分类号： G06F15/16 , G06F9/48 , G06F11/10 , G06F11/30 , G06F11/32 , G06F15/177 , G06F17/17 , G06F7/00 , G06F9/46
CPC分类号： G06F11/3072 , G06F11/10 , G06F17/17 , G06F11/327 , G06F2201/86 , G06F2201/88
摘要： A method and apparatus is provided for generating an interrupt signal in a data processing system, the interrupt signal being supplied to a control processor of the system to indicate the occurrence of any of a plurality of predetermined events in the system. The method and apparatus operate by: writing data to at least one memory location of a plurality of pairs of memory locations A,B of the system in dependence upon the event to be indicated, the pairs of memory locations A,B being predefined in the system for respective ones of the events; reading data from the pairs of memory locations A,B; processing the data read from each pair of memory locations A,B to generate interrupt data indicative of whether the associated event has occurred, and if so transmitting an interrupt signal to the control processor; and writing the interrupt data corresponding to the events to respective third memory locations C, the third memory locations C being predefined in the control processor for the events. On receipt of an interrupt signal, the control processor reads the interrupt data in the third memory locations C to determine the event indicated by the interrupt signal.
摘要翻译：提供了一种用于在数据处理系统中产生中断信号的方法和装置，所述中断信号被提供给系统的控制处理器，以指示系统中多个预定事件中的任何一个发生。该方法和装置通过以下方式操作：根据要指示的事件将数据写入系统的多对存储器位置A，B的至少一个存储器位置，存储器位置A，B在系统为各自的事件; 从存储单元对A，B中读取数据; 处理从每对存储器位置A，B读取的数据，以产生指示相关联的事件是否已经发生的中断数据，并且如果发送中断信号到控制处理器; 并将与事件相对应的中断数据写入相应的第三存储器位置C，在控制处理器中为事件预定义第三存储单元C. 在接收到中断信号时，控制处理器读取第三存储器位置C中的中断数据，以确定由中断信号指示的事件。

3. 发明授权

US5712808A Digital signal processing 失效
公开(公告)号：US5712808A
公开(公告)日：1998-01-27
申请号：US510167
申请日：1995-08-02
申请人： Peter Charles Eastty , Tetsuya Konishi , Conrad Charles Cooke
发明人： Peter Charles Eastty , Tetsuya Konishi , Conrad Charles Cooke
IPC分类号： G10L19/00 , G10H1/12 , H03H17/02 , H03H17/04 , G06F17/10
CPC分类号： G10H1/125 , H03H17/0294 , H03H17/04 , G10H2250/101 , G10H2250/121 , G10H2250/545
摘要： Digital signal processing (e.g. filtering) apparatus comprises pipelined digital signal processing means for generating each output sample of an output digital signal from input samples of an input digital signal by combining the input samples with a plurality of subsets of a set of filter coefficients associated with that output sample during a respective plurality of sample periods of the input digital signal; and coefficient generating means for supplying sets of filter coefficients to the signal processing means in response to the current state of a filter control signal. The coefficient generating means is operable to supply the plurality of subsets of each set of filter coefficients to the signal processing means during the respective plurality of sample periods of the input digital signal.

4. 发明授权

US5881077A Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：US5881077A
公开(公告)日：1999-03-09
申请号：US845559
申请日：1997-04-24
申请人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
发明人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
IPC分类号： G06F15/16 , G06F9/48 , G06F11/10 , G06F11/30 , G06F11/32 , G06F15/177 , G06F17/17 , G06F11/00
CPC分类号： G06F11/3072 , G06F11/10 , G06F17/17 , G06F11/327 , G06F2201/86 , G06F2201/88
摘要： A method and apparatus is provided for generating an interrupt signal in a data processing system, the interrupt signal being supplied to a control processor of the system to indicate the occurrence of any of a plurality of predetermined events in the system. The method and apparatus operate by: writing data to at least one memory location of a plurality of pairs of memory locations A,B of the system in dependence upon the event to be indicated, the pairs of memory locations A,B being predefined in the system for respective ones of the events; reading data from the pairs of memory locations A,B; processing the data read from each pair of memory locations A,B to generate interrupt data indicative of whether the associated event has occurred, and if so transmitting an interrupt signal to the control processor; and writing the interrupt data corresponding to the events to respective third memory locations C, the third memory locations C being predefined in the control processor for the said events. On receipt of an interrupt signal, the control processor reads the interrupt data in the third memory locations C to determine the event indicated by the interrupt signal.
摘要翻译：提供了一种用于在数据处理系统中产生中断信号的方法和装置，所述中断信号被提供给系统的控制处理器，以指示系统中多个预定事件中的任何一个发生。该方法和装置通过以下方式操作：根据要指示的事件将数据写入系统的多对存储器位置A，B的至少一个存储器位置，存储器位置A，B在系统为各自的事件; 从存储单元对A，B中读取数据; 处理从每对存储器位置A，B读取的数据，以产生指示相关联的事件是否已经发生的中断数据，并且如果发送中断信号到控制处理器; 并将对应于事件的中断数据写入相应的第三存储器位置C，在控制处理器中为所述事件预定义第三存储单元C. 在接收到中断信号时，控制处理器读取第三存储器位置C中的中断数据，以确定由中断信号指示的事件。

5. 发明授权

US5877971A Digital signal processing 失效
标题翻译：数字信号处理
公开(公告)号：US5877971A
公开(公告)日：1999-03-02
申请号：US947289
申请日：1997-10-07
申请人： Peter Charles Eastty , Tetsuya Konishi , Conrad Charles Cooke
发明人： Peter Charles Eastty , Tetsuya Konishi , Conrad Charles Cooke
IPC分类号： G10L19/00 , G10H1/12 , H03H17/02 , H03H17/04 , G06F17/10
CPC分类号： G10H1/125 , H03H17/0294 , H03H17/04 , G10H2250/101 , G10H2250/121 , G10H2250/545
摘要： Digital signal processing (e.g. filtering) apparatus comprises pipelined digital signal processing means for generating each output sample of an output digital signal from input samples of an input digital signal by combining the input samples with a plurality of subsets of a set of filter coefficients associated with that output sample during a respective plurality of sample periods of the input digital signal; and coefficient generating means for supplying sets of filter coefficients to the signal processing means in response to the current state of a filter control signal. The coefficient generating means is operable to supply the plurality of subsets of each set of filter coefficients to the signal processing means during the respective plurality of sample periods of the input digital signal.
摘要翻译：数字信号处理（例如滤波）装置包括流水线数字信号处理装置，用于通过将输入样本与一组与滤波系数相关联的多个子集组合而从输入数字信号的输入样本产生输出数字信号的每个输出样本在输入数字信号的相应多个采样周期期间该输出采样; 以及系数产生装置，用于响应于滤波器控制信号的当前状态向信号处理装置提供滤波器系数集合。系数产生装置可操作以在输入数字信号的相应多个采样周期期间将每组滤波器系数的多个子集提供给信号处理装置。

6. 发明授权

US5802385A Array processing system with each processor including router and which selectively delays input/output of individual processors in response delay instructions 失效
标题翻译：阵列处理系统，每个处理器包括路由器，并且在响应延迟指令中选择性地延迟单个处理器的输入/输出
公开(公告)号：US5802385A
公开(公告)日：1998-09-01
申请号：US515837
申请日：1995-08-16
申请人： Rodney Hugh Densham , Peter Charles Eastty , Conrad Charles Cooke
发明人： Rodney Hugh Densham , Peter Charles Eastty , Conrad Charles Cooke
IPC分类号： G06F15/16 , G06F15/177 , G06F15/80 , H04H60/04 , G06F15/82
CPC分类号： H04H60/04
摘要： In one aspect, the invention provides parallel processing apparatus comprising an array of data processors 4. arranged to operate synchronously, and a plurality of data buses. Each data processor 4 has first and second I/O means 16H, 16V for transfer of data between the processor 4 and respective data buses H,V a plurality of processors 4 being connected to each of the data buses H,V and each processor 4 being connected, via said I/O means 16H, 16V, to a different pair of data buses H,V. Each processor 4 includes selectively operable routing means 32H, 32V for interconnecting the first and second I/O means 16H, 16V to transfer data between the buses H,V connected thereto.
摘要翻译：一方面，本发明提供并行处理装置，其包括布置成同步操作的数据处理器阵列4和多个数据总线。每个数据处理器4具有用于在处理器4和相应的数据总线H，V之间传送数据的第一和第二I / O装置16H，16V，多个处理器4连接到每个数据总线H，V和每个处理器4 通过所述I / O装置16H，16V连接到不同的一对数据总线H，V。每个处理器4包括用于互连第一和第二I / O装置16H，16V的选择性可操作的路由装置32H，32V，以在连接到其之间的总线H，V之间传送数据。

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