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    • 9. 发明授权
    • Method and process for testing the reliability of integrated circuit
(IC) chips and novel IC circuitry for accomplishing same
    • 用于测试集成电路(IC)芯片和新型IC电路的可靠性的方法和过程以实现其
    • US4918385A
    • 1990-04-17
    • US307727
    • 1989-02-07
    • Robert W. Shreeve
    • Robert W. Shreeve
    • G01R31/26G01R31/28G01R31/30G01R31/317
    • G01R31/2856G01R31/2642G01R31/30G01R31/31701
    • Disclosed herein is a method and circuit useful in the testing of integrated circuit chips. On-chip test circuitry is provided at a selected location on an IC chip and energized while the chips are still mounted on a lead frame member, wound on reels and heated in an oven. Advantageously, the continuous lead frame member may be a tape automated bond (TAB bond) flexible circuit which is adapted for gang bonding to a large plurality of ICs before being wound on reels. In a preferred test circuit embodiment, the conductive on-off state of digital address circuity is controlled by applying a test signal potential to an input test pad and through a fuse to a common test circuit junction. This junction is in turn connected between a transistor and diode in a series control network which is operative to control the conductive state of the address circuitry. This network enables the input test pad to be used as both a test signal input connection and a ground connection for the IC test circuit.
    • 这里公开了一种在集成电路芯片的测试中有用的方法和电路。 片上测试电路设置在IC芯片上的选定位置并通电,同时芯片仍然安装在引线框架构件上,缠绕在卷轴上并在烘箱中加热。 有利地,连续引线框架构件可以是带状自动接合(TAB键)柔性电路,其适于在缠绕在卷轴上之前与大量多个IC结合。 在优选的测试电路实施例中,通过将测试信号电位施加到输入测试焊盘并通过熔丝到公共测试电路结来控制数字地址电路的导通开 - 关状态。 该结又连接在串联控制网络中的晶体管和二极管之间,该串联控制网络可操作地控制地址电路的导通状态。 该网络使得输入测试板既可用作IC测试电路的测试信号输入连接和接地连接。
    • 10. 发明授权
    • Tab frame and process of testing same
    • Tab框和测试过程相同
    • US5121053A
    • 1992-06-09
    • US547667
    • 1990-07-03
    • Robert W. ShreeveMelissa D. Boyd
    • Robert W. ShreeveMelissa D. Boyd
    • G01R31/28H01L23/495
    • H01L23/49572G01R31/2886H01L2924/0002Y10T307/647
    • A tape automated bonding (TAB) frame and a process for testing the same. The frame is designed to receive a die, an integrated chip or other similar components having output leads. The frame generally comprises a relatively thin film of dielectric material, a pattern of substantially adjacent inner lead bonds, a pattern of substantially adjacent outer lead bonds for providing input/output ports to the die, and a pattern of substantilly adjacent probe points for providing test points to the frame and the die thereon. A generally flat and rigid plate is mounted on a prober for supporting both a cut-out portion of the frame and the die thereon. The testing process includes the steps of excising the die from the frame in the form of a coupon, such that the coupon contains the pattern of scrap probe points on the TAB frame and the die; placing the excised coupon onto the prober; aligning the coupon; and testing the coupon and the die.
    • 胶带自动粘贴(TAB)框架和测试过程。 该框架设计用于接收管芯,集成芯片或具有输出引线的其它类似部件。 该框架通常包括相对薄的电介质材料,基本上相邻的内部引线接合的图案,用于向管芯提供输入/输出端口的基本上相邻的外部引线键合的图案,以及用于提供测试的基本相邻探针点的图案 指向框架和其上的模具。 大致平坦且刚性的板安装在探测器上,用于支撑框架的切口部分和模具。 测试过程包括以试件形式从模具中切出模具的步骤,使得试样包含TAB框架和模具上的废料探针点的图案; 将切割的优惠券放在探险者身上; 对齐优惠券; 并测试优惠券和模具。