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1. 发明授权

US07338865B2 Method for manufacturing dual work function gate electrodes through local thickness-limited silicidation 有权
标题翻译：通过局部厚度限制硅化物制造双功能功能栅电极的方法
公开(公告)号：US07338865B2
公开(公告)日：2008-03-04
申请号：US10897846
申请日：2004-07-23
申请人： Robert W. Murto , Luigi Colombo , Mark R. Visokay
发明人： Robert W. Murto , Luigi Colombo , Mark R. Visokay
IPC分类号： H01L21/8234
CPC分类号： H01L21/823835 , H01L21/823842
摘要： The present invention provides a method of manufacturing a semiconductor device. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a gate electrode (135) that includes a metal silicide layer 135a over which is located a silicon gate layer (135b) together which have a work function associated therewith, and a second transistor (125) located over the semiconductor substrate (110) and proximate the first transistor (120), wherein the second transistor (125) also includes a gate electrode (160) that includes a metal silicide layer (160a) over which is located a silicon gate layer (160b) together which have a different work function from that of the first gate electrode (135) associated therewith.
摘要翻译：本发明提供一种制造半导体器件的方法。除了其它可能的元件之外，半导体器件（100）包括位于半导体衬底（110）上方的第一晶体管（120），其中第一晶体管（120）具有包括金属硅化物层135a的栅电极（135）位于硅栅极层（135b）上，其具有与其相关联的功函数;以及第二晶体管（125），位于半导体衬底（110）之上并且靠近第一晶体管（120），其中第二晶体管 125）还包括栅电极（160），其包括金属硅化物层（160a），栅极电极（160a）位于硅栅极层（160b）上，其具有与第一栅电极（135）的功函数不同的功函随之而来。

2. 发明申请

US20100155860A1 TWO STEP METHOD TO CREATE A GATE ELECTRODE USING A PHYSICAL VAPOR DEPOSITED LAYER AND A CHEMICAL VAPOR DEPOSITED LAYER 审中-公开
标题翻译：使用物理蒸气沉积层和化学气相沉积层创建门电极的两步法
公开(公告)号：US20100155860A1
公开(公告)日：2010-06-24
申请号：US12344046
申请日：2008-12-24
申请人： Luigi Colombo , James J. Chambers , Mark R. Visokay , Majid Mansoori
发明人： Luigi Colombo , James J. Chambers , Mark R. Visokay , Majid Mansoori
IPC分类号： H01L29/43 , H01L21/283 , H01L21/336 , C23C14/34
CPC分类号： H01L21/28088 , H01L21/28079 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/66545
摘要： One embodiment of the present invention relates a semiconductor device formed by utilizing a two step deposition method for forming a gate electrode without causing damages to an underlying gate dielectric material. In one embodiment, a first layer of gate electrode material (first gate electrode layer) is formed onto the surface of a gate dielectric material using a deposition that does not damage the gate dielectric material (e.g., physical vapor deposition) thereby resulting in a damage free interface between the gate dielectric material and the gate electrode material. A second layer of gate electrode material (second gate electrode layer) is then formed onto the first layer of gate electrode material using a chemical deposition method that provides increased deposition control (e.g., good layer uniformity, impurity control, etc.). The first and second gate electrode layers are then selectively patterned to cumulatively form a semiconductor device's gate electrode.
摘要翻译：本发明的一个实施例涉及通过利用用于形成栅电极的两步沉积方法形成的半导体器件，而不会对下面的栅介质材料造成损害。在一个实施例中，使用不损坏栅极电介质材料（例如，物理气相沉积）的沉积，在栅极电介质材料的表面上形成第一层栅电极材料（第一栅电极层），从而导致损坏栅介电材料和栅电极材料之间的自由界面。然后使用提供增加的沉积控制（例如，良好的层均匀性，杂质控制等）的化学沉积方法将第二层栅电极材料（第二栅极电极层）形成在第一层栅电极材料层上。然后，第一和第二栅极电极层被选择性地图案化以累积地形成半导体器件的栅电极。

3. 发明授权

US07351626B2 Method for controlling defects in gate dielectrics 有权
标题翻译：控制栅极电介质缺陷的方法
公开(公告)号：US07351626B2
公开(公告)日：2008-04-01
申请号：US10739617
申请日：2003-12-18
申请人： Luigi Colombo , James J. Chambers , Mark R. Visokay , Antonio L. P. Rotondaro
发明人： Luigi Colombo , James J. Chambers , Mark R. Visokay , Antonio L. P. Rotondaro
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/02318 , C23C16/56 , H01L21/02323 , H01L21/28185 , H01L21/28194 , H01L21/3143 , H01L21/31608 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/318 , H01L29/518 , H01L29/78
摘要： A method for improving high-κ gate dielectric film (104) properties. The high-κ film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.
摘要翻译：一种改善高卡门电介质膜（104）性能的方法。对高卡帕膜（104）进行两步退火处理。第一退火在具有低分压氧化剂的还原环境（106）中进行，以促进膜弛豫并增加副产物扩散和解吸附。第二次退火在具有低分压还原剂的氧化环境（108）中进行以除去缺陷和杂质。

4. 发明授权

US06809370B1 High-k gate dielectric with uniform nitrogen profile and methods for making the same 有权
标题翻译：具有均匀氮分布的高k栅极电介质及其制造方法
公开(公告)号：US06809370B1
公开(公告)日：2004-10-26
申请号：US10632230
申请日：2003-07-31
申请人： Luigi Colombo , Manuel Quevedo-Lopez , James J. Chambers , Mark R. Visokay , Antonio L. P. Rotondaro
发明人： Luigi Colombo , Manuel Quevedo-Lopez , James J. Chambers , Mark R. Visokay , Antonio L. P. Rotondaro
IPC分类号： H01L27108
CPC分类号： H01L29/518 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/6659 , H01L29/7833
摘要： High-k transistor gate structures and fabrication methods therefor are provided, wherein a gate dielectric interface region near a semiconductor substrate is provided with very little or no nitrogen, while the bulk high-k dielectric is provided with a uniform nitrogen concentration.
摘要翻译：提供了高k晶体管栅极结构及其制造方法，其中在半导体衬底附近的栅极电介质界面区域设置有非常少的或不具有氮的，而本体高k电介质具有均匀的氮浓度。

5. 发明申请

US20120231590A1 Method of Setting a Work Function of a Fully Silicided Semiconductor Device, and Related Device 审中-公开
标题翻译：设置完全硅化半导体器件的功能的方法及相关器件
公开(公告)号：US20120231590A1
公开(公告)日：2012-09-13
申请号：US13474927
申请日：2012-05-18
申请人： Luigi Colombo , Mark R. Visokay , James J. Chambers
发明人： Luigi Colombo , Mark R. Visokay , James J. Chambers
IPC分类号： H01L21/28 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/28079 , H01L21/28097 , H01L21/28176 , H01L21/28518 , H01L21/76819 , H01L21/823842
摘要： A method of setting a work function of a filly silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a suicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the suicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction.
摘要翻译：一种设置硅化半导体器件功能的方法及相关器件。示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅极堆叠包括电介质层，介电层上的硅化物层，其限定金属 - 电介质层界面，以及硅化物层层），在栅极堆叠上沉积金属层，退火以引起多晶硅层和金属层之间的反应，以及通过反应将功函数赋予掺杂剂输送到金属 - 介电层界面。

6. 发明申请

US20110111586A1 Method of Setting a Work Function of a Fully Silicided Semiconductor Device, and Related Device 审中-公开
标题翻译：设置完全硅化半导体器件的功能的方法及相关器件
公开(公告)号：US20110111586A1
公开(公告)日：2011-05-12
申请号：US13004162
申请日：2011-01-11
申请人： Luigi Colombo , Mark R. Visokay , James J. Chambers
发明人： Luigi Colombo , Mark R. Visokay , James J. Chambers
IPC分类号： H01L21/3205
CPC分类号： H01L21/823835 , H01L21/28079 , H01L21/28097 , H01L21/28176 , H01L21/28518 , H01L21/76819 , H01L21/823842
摘要： A method of setting a work function of a fully silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a silicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the silicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction.
摘要翻译：一种设置完全硅化半导体器件的功能的方法及相关器件。示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅极堆叠包括电介质层，介电层上的硅化物层，其限定金属 - 电介质层界面，以及硅化物上的多晶硅层层），在栅极堆叠上沉积金属层，退火以引起多晶硅层和金属层之间的反应，以及通过反应将功函数赋予掺杂剂输送到金属 - 电介质层界面。

7. 发明授权

US07601578B2 Defect control in gate dielectrics 有权
标题翻译：栅极电介质缺陷控制
公开(公告)号：US07601578B2
公开(公告)日：2009-10-13
申请号：US11924132
申请日：2007-10-25
申请人： Luigi Colombo , James J. Chambers , Mark R. Visokay , Antonio Luis Pacheco Rotondaro
发明人： Luigi Colombo , James J. Chambers , Mark R. Visokay , Antonio Luis Pacheco Rotondaro
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/02318 , C23C16/56 , H01L21/02323 , H01L21/28185 , H01L21/28194 , H01L21/3143 , H01L21/31608 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/318 , H01L29/518 , H01L29/78
摘要： A method for improving high-κ gate dielectric film (104) properties. The high-κ film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.
摘要翻译：一种改善高卡门电介质膜（104）性能的方法。对高卡帕膜（104）进行两步退火处理。第一退火在具有低分压氧化剂的还原环境（106）中进行，以促进膜弛豫并增加副产物扩散和解吸附。第二次退火在具有低分压还原剂的氧化环境（108）中进行以除去缺陷和杂质。

8. 发明授权

US07291890B2 Gate dielectric and method 有权
标题翻译：栅极电介质和方法
公开(公告)号：US07291890B2
公开(公告)日：2007-11-06
申请号：US11339393
申请日：2006-01-25
申请人： Mark R. Visokay , Antonio L. P. Rotondaro , Luigi Colombo
发明人： Mark R. Visokay , Antonio L. P. Rotondaro , Luigi Colombo
IPC分类号： H01L29/76
CPC分类号： H01L21/823857 , H01L21/823842
摘要： A MOSFET structure with high-k gate dielectric layer and silicon or metal gates, amorphizing treatment of the high-k gate dielectric layer as with a plasma or ion implantation.
摘要翻译：具有高k栅极电介质层和硅或金属栅极的MOSFET结构，与等离子体或离子注入一起对高k栅极介电层进行非晶化处理。

9. 发明授权

US07229873B2 Process for manufacturing dual work function metal gates in a microelectronics device 有权
标题翻译：在微电子器件中制造双功能金属栅极的工艺
公开(公告)号：US07229873B2
公开(公告)日：2007-06-12
申请号：US11200741
申请日：2005-08-10
申请人： Luigi Colombo , James J. Chambers , Mark R. Visokay
发明人： Luigi Colombo , James J. Chambers , Mark R. Visokay
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/04 , H01L21/4763 , H01L21/3205
CPC分类号： H01L21/823842 , H01L29/66545
摘要： The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305. The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.
摘要翻译：本发明提供一种形成双功函数金属栅极微电子器件200的方法。在一个方面，该方法包括形成nMOS和pMOS堆叠栅极结构315a和315b。 nMOS和pMOS堆叠栅极结构315a和315b各自包括栅极电介质205，位于栅极电介质205上方的第一金属层305和位于第一金属层305上方的牺牲栅极层310。该方法还包括在nMOS或pMOS堆叠栅极结构中的至少一个中去除牺牲栅极层310，从而形成栅极开口825并修改栅极开口825内的第一金属层305以形成具有所需工作的栅电极功能。

10. 发明授权

US07226826B2 Semiconductor device having multiple work functions and method of manufacture therefor 有权
标题翻译：具有多种功能的半导体装置及其制造方法
公开(公告)号：US07226826B2
公开(公告)日：2007-06-05
申请号：US10826516
申请日：2004-04-16
申请人： Husam N. Alshareef , Mark R. Visokay , Antonio Luis Pacheco Rotondaro , Luigi Colombo
发明人： Husam N. Alshareef , Mark R. Visokay , Antonio Luis Pacheco Rotondaro , Luigi Colombo
IPC分类号： H01L21/8238
CPC分类号： H01L21/321 , H01L21/28079 , H01L21/823835 , H01L21/823842
摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a metal gate electrode (135) having a work function, and a second transistor (160) located over the semiconductor substrate (110) and proximate the first transistor (120), wherein the second transistor (160) has a plasma altered metal gate electrode (175) having a different work function.
摘要翻译：本发明提供一种半导体器件及其制造方法以及集成电路的制造方法。半导体器件（100）以及其他可能的元件包括位于半导体衬底（110）上方的第一晶体管（120），其中第一晶体管（120）具有具有功函数的金属栅电极（135）第二晶体管（160）位于半导体衬底（110）上并且靠近第一晶体管（120），其中第二晶体管（160）具有具有不同功函数的等离子体改变的金属栅电极（175）。

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