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1. 发明授权

US07601578B2 Defect control in gate dielectrics 有权
标题翻译：栅极电介质缺陷控制
公开(公告)号：US07601578B2
公开(公告)日：2009-10-13
申请号：US11924132
申请日：2007-10-25
申请人： Luigi Colombo , James J. Chambers , Mark R. Visokay , Antonio Luis Pacheco Rotondaro
发明人： Luigi Colombo , James J. Chambers , Mark R. Visokay , Antonio Luis Pacheco Rotondaro
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/02318 , C23C16/56 , H01L21/02323 , H01L21/28185 , H01L21/28194 , H01L21/3143 , H01L21/31608 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/318 , H01L29/518 , H01L29/78
摘要： A method for improving high-κ gate dielectric film (104) properties. The high-κ film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.
摘要翻译：一种改善高卡门电介质膜（104）性能的方法。对高卡帕膜（104）进行两步退火处理。第一退火在具有低分压氧化剂的还原环境（106）中进行，以促进膜弛豫并增加副产物扩散和解吸附。第二次退火在具有低分压还原剂的氧化环境（108）中进行以除去缺陷和杂质。

2. 发明授权

US07226826B2 Semiconductor device having multiple work functions and method of manufacture therefor 有权
标题翻译：具有多种功能的半导体装置及其制造方法
公开(公告)号：US07226826B2
公开(公告)日：2007-06-05
申请号：US10826516
申请日：2004-04-16
申请人： Husam N. Alshareef , Mark R. Visokay , Antonio Luis Pacheco Rotondaro , Luigi Colombo
发明人： Husam N. Alshareef , Mark R. Visokay , Antonio Luis Pacheco Rotondaro , Luigi Colombo
IPC分类号： H01L21/8238
CPC分类号： H01L21/321 , H01L21/28079 , H01L21/823835 , H01L21/823842
摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a metal gate electrode (135) having a work function, and a second transistor (160) located over the semiconductor substrate (110) and proximate the first transistor (120), wherein the second transistor (160) has a plasma altered metal gate electrode (175) having a different work function.
摘要翻译：本发明提供一种半导体器件及其制造方法以及集成电路的制造方法。半导体器件（100）以及其他可能的元件包括位于半导体衬底（110）上方的第一晶体管（120），其中第一晶体管（120）具有具有功函数的金属栅电极（135）第二晶体管（160）位于半导体衬底（110）上并且靠近第一晶体管（120），其中第二晶体管（160）具有具有不同功函数的等离子体改变的金属栅电极（175）。

3. 发明授权

US07015088B2 High-K gate dielectric defect gettering using dopants 有权
标题翻译：使用掺杂剂的高K栅介质缺陷吸杂
公开(公告)号：US07015088B2
公开(公告)日：2006-03-21
申请号：US10335560
申请日：2002-12-31
申请人： Luigi Colombo , James J. Chambers , Antonio Luis Pacheco Rotondaro
发明人： Luigi Colombo , James J. Chambers , Antonio Luis Pacheco Rotondaro
IPC分类号： H01L21/00 , H01L21/8242
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/517 , H01L29/518 , H01L29/6659
摘要： One or more aspects of the present invention relate to forming a transistor while passivating electrically active defects associated with a top portion of a layer of high-k dielectric material. The layer of high-k dielectric material is utilized to establish a high-k gate dielectric in the transistor. A gate electrode layer is formed over the layer of high-k dielectric material, and is patterned to form a gate structure that includes a gate electrode and the high-k gate dielectric. The electrically active defects are passivated utilizing materials containing dopants that are attracted to and neutralize the defects. The passivated defects thus do not interfere with other transistor doping processes (e.g., forming source and drain regions) and do not adversely affect resulting semiconductor device performance, reliability and yield.
摘要翻译：本发明的一个或多个方面涉及形成晶体管，同时钝化与高k电介质材料层的顶部相关联的电活性缺陷。高k介电材料层用于在晶体管中建立高k栅极电介质。栅电极层形成在高k电介质材料层上，并被图案化以形成包括栅电极和高k栅电介质的栅结构。使用含有被吸引并中和缺陷的掺杂剂的材料来钝化电活性缺陷。钝化的缺陷因此不干扰其它晶体管掺杂过程（例如，形成源极和漏极区），并且不会对所得到的半导体器件性能，可靠性和产量产生不利影响。

4. 发明授权

US07601577B2 Work function control of metals 有权
标题翻译：金属工作功能控制
公开(公告)号：US07601577B2
公开(公告)日：2009-10-13
申请号：US11870631
申请日：2007-10-11
申请人： James Joseph Chambers , Mark Robert Visokay , Luigi Colombo , Antonio Luis Pacheco Rotondaro
发明人： James Joseph Chambers , Mark Robert Visokay , Luigi Colombo , Antonio Luis Pacheco Rotondaro
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/4763 , H01L21/3205
CPC分类号： H01L21/823842
摘要： Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.
摘要翻译：公开了具有不同功函数的金属栅极晶体管。在一个示例中，第一金属是“中间间隙”金属，分别在第一和第二区域中被第二和第三金属操纵，以在不同区域中沿相反方向移动第一金属的功函数。在不同区域中产生的功函数对应于将要形成的不同类型的晶体管。

5. 发明授权

US07071519B2 Control of high-k gate dielectric film composition profile for property optimization 有权
标题翻译：控制高k栅极电介质膜组成轮廓的性能优化
公开(公告)号：US07071519B2
公开(公告)日：2006-07-04
申请号：US10338310
申请日：2003-01-08
申请人： Luigi Colombo , Mark Visokay , James Joseph Chambers , Antonio Luis Pacheco Rotondaro
发明人： Luigi Colombo , Mark Visokay , James Joseph Chambers , Antonio Luis Pacheco Rotondaro
IPC分类号： H01L29/94
CPC分类号： H01L21/02271 , H01L21/28194 , H01L21/3142 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/78
摘要： Methods and systems are disclosed that facilitate formation of dielectric layers having a particular composition profile by forming the dielectric layer as a number of sub-layers. The sub-layers are thin enough so that specific relative compositions can be achieved for each layer and, therefore, the sub-layers collectively yield a dielectric layer with a particular profile. The formation of individual sub layers is accomplished by controlling one or more processing parameters for a chemical vapor deposition process that affect relative compositions. Some processing parameters that can be employed include wafer temperature, pressure, and precursor flow rate.
摘要翻译：公开了通过将介电层形成多个子层来促进形成具有特定组成分布的电介质层的方法和系统。子层足够薄，使得可以为每个层实现特定的相对组成，因此，子层共同产生具有特定轮廓的介电层。单个子层的形成通过控制影响相对组成的化学气相沉积工艺的一个或多个处理参数来实现。可采用的一些加工参数包括晶片温度，压力和前体流速。

6. 发明授权

US07291527B2 Work function control of metals 有权
标题翻译：金属工作功能控制
公开(公告)号：US07291527B2
公开(公告)日：2007-11-06
申请号：US11220451
申请日：2005-09-07
申请人： James Joseph Chambers , Mark Robert Visokay , Luigi Colombo , Antonio Luis Pacheco Rotondaro
发明人： James Joseph Chambers , Mark Robert Visokay , Luigi Colombo , Antonio Luis Pacheco Rotondaro
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823842
摘要： Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.
摘要翻译：公开了具有不同功函数的金属栅极晶体管。在一个示例中，第一金属是“中间间隙”金属，分别在第一和第二区域中被第二和第三金属操纵，以在不同区域中沿相反方向移动第一金属的功函数。在不同区域中产生的功函数对应于将要形成的不同类型的晶体管。

7. 发明授权

US06750126B1 Methods for sputter deposition of high-k dielectric films 有权
标题翻译：溅射沉积高k电介质膜的方法
公开(公告)号：US06750126B1
公开(公告)日：2004-06-15
申请号：US10338276
申请日：2003-01-08
申请人： Mark Visokay , James Joseph Chambers , Luigi Colombo , Antonio Luis Pacheco Rotondaro
发明人： Mark Visokay , James Joseph Chambers , Luigi Colombo , Antonio Luis Pacheco Rotondaro
IPC分类号： H01L213205
CPC分类号： H01L21/28202 , H01L21/28035 , H01L21/28194 , H01L21/314 , H01L21/3143 , H01L21/31645 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6659
摘要： Methods are disclosed for fabricating transistor gate structures and high-k dielectric layers therefor by sputter deposition, in which nitridation and/or oxidation or other adverse reaction of the semiconductor material is reduced or minimized by reducing the bombardment of the semiconductor body by positively charged reactive ions such as oxygen ions or nitrogen ions during the sputter deposition process. The sputtering operation may be a two-step process in which ionic bombardment of the semiconductor material is minimized in an initial deposition step to form a first layer portion covering the semiconductor body, and the second step completes the desired high-k dielectric layer. Mitigation of unwanted nitridation and/or oxidation or other adverse reaction is achieved through one, some, or all of high sputtering deposition pressure, repulsive wafer biasing, increased wafer-plasma spacing, low partial pressures for reactant gases, and low sputtering powers or power densities.
摘要翻译：公开了用于通过溅射沉积来制造晶体管栅极结构和高k电介质层的方法，其中半导体材料的氮化和/或氧化或其它不利反应被减小或最小化，通过减少半导体主体的带正电荷的反应离子如氧离子或氮离子在溅射沉积过程中。溅射操作可以是在初始沉积步骤中使半导体材料的离子轰击最小化以形成覆盖半导体本体的第一层部分的两步法，并且第二步骤完成所需的高k电介质层。通过高溅射沉积压力，排斥晶片偏置，增加的晶片 - 等离子体间隔，反应气体的低分压以及低溅射功率或功率的一种，一些或全部来实现减少不希望的氮化和/或氧化或其它不利反应密度

8. 发明授权

US06696332B2 Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing 有权
标题翻译：双层沉积以避免在高K栅介质处理期间的不希望的界面反应
公开(公告)号：US06696332B2
公开(公告)日：2004-02-24
申请号：US10176596
申请日：2002-06-21
申请人： Mark Robert Visokay , Antonio Luis Pacheco Rotondaro , Luigi Colombo
发明人： Mark Robert Visokay , Antonio Luis Pacheco Rotondaro , Luigi Colombo
IPC分类号： H01L218238
CPC分类号： H01L21/28185 , H01L21/2652 , H01L21/28194 , H01L21/28202 , H01L21/28238 , H01L21/28291 , H01L29/513 , H01L29/517 , H01L29/518
摘要： Methods are disclosed for forming gate dielectrics for MOSFET transistors, wherein a bilayer deposition of a nitride layer and an oxide layer are used to form a gate dielectric stack. The nitride layer is formed on the substrate to prevent oxidation of the substrate material during deposition of the oxide layer, thereby avoiding or mitigating formation of low-k interfacial layer.
摘要翻译：公开了用于形成用于MOSFET晶体管的栅极电介质的方法，其中使用氮化物层和氧化物层的双层沉积来形成栅极电介质叠层。在衬底上形成氮化物层以防止氧化物层沉积期间衬底材料的氧化，从而避免或减轻低k界面层的形成。

9. 发明授权

US06803611B2 Use of indium to define work function of p-type doped polysilicon 有权
公开(公告)号：US06803611B2
公开(公告)日：2004-10-12
申请号：US10336563
申请日：2003-01-03
申请人： Antonio Luis Pacheco Rotondaro , James J. Chambers , Amitabh Jain
发明人： Antonio Luis Pacheco Rotondaro , James J. Chambers , Amitabh Jain
IPC分类号： H01L2710
CPC分类号： H01L29/4925 , H01L21/28035 , H01L21/2807
摘要： The present invention pertains to formation of a PMOS transistor wherein a layer of silicon or SiGe inhibits p-type dopant from entering into an underlying gate dielectric layer. The p-type dopant can be added to a gate electrode material that overlies the silicon or SiGe layer and can diffuse down toward the silicon or SiGe layer. The layer of silicon or SiGe may be formed to a thickness of about 5 to 120 nanometers and doped with a dopant, such as indium (In), for example, to deter the p-type dopant from passing through the silicon or SiGe layer. The dopant may have a peak concentration within the layer of silicon or SiGe near the interface of the silicon or SiGe layer with the underlying layer of gate dielectric material. Allowing the gate electrode to be doped with the p-type dopant (e.g., boron) facilitates forming the transistor with an associated work function having a desired value (e.g., coincident with a Fermi level of about 4.8 to about 5.6 electron volts).

10. 发明授权

US07026218B2 Use of indium to define work function of p-type doped polysilicon 有权
标题翻译：使用铟来定义p型掺杂多晶硅的功函数
公开(公告)号：US07026218B2
公开(公告)日：2006-04-11
申请号：US10865342
申请日：2004-06-10
申请人： Antonio Luis Pacheco Rotondaro , James J. Chambers , Amitabh Jain
发明人： Antonio Luis Pacheco Rotondaro , James J. Chambers , Amitabh Jain
IPC分类号： H01L21/336
CPC分类号： H01L29/4925 , H01L21/28035 , H01L21/2807
摘要： The present invention pertains to formation of a PMOS transistor wherein a layer of silicon or SiGe inhibits p-type dopant from entering into an underlying gate dielectric layer. The p-type dopant can be added to a gate electrode material that overlies the silicon or SiGe layer and can diffuse down toward the silicon or SiGe layer. The layer of silicon or SiGe may be formed to a thickness of about 5 to 120 nanometers and doped with a dopant, such as indium (In), for example, to deter the p-type dopant from passing through the silicon or SiGe layer. The dopant may have a peak concentration within the layer of silicon or SiGe near the interface of the silicon or SiGe layer with the underlying layer of gate dielectric material. Allowing the gate electrode to be doped with the p-type dopant (e.g., boron) facilitates forming the transistor with an associated work function having a desired value (e.g., coincident with a Fermi level of about 4.8 to about 5.6 electron volts).
摘要翻译：本发明涉及一种PMOS晶体管的形成，其中一层硅或SiGe抑制p型掺杂剂进入下面的栅介质层。可以将p型掺杂剂添加到覆盖硅或SiGe层的栅电极材料中，并且可以向硅或SiGe层扩散。硅或SiGe层可以形成为约5至120纳米的厚度，并掺杂有例如铟（In）的掺杂剂，以阻止p型掺杂剂通过硅或SiGe层。掺杂剂可以在硅或SiGe层的界面附近与硅介电材料的下层之间的硅或SiGe层内具有峰值浓度。允许栅电极掺杂有p型掺杂剂（例如硼）有助于以具有期望值（例如，与约4.8至约5.6电子伏特的费米能级一致）的相关功函数形成晶体管。

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