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1. 发明授权

US4994995A Bit-serial division method and apparatus 失效
标题翻译：位串行分割方法和装置
公开(公告)号：US4994995A
公开(公告)日：1991-02-19
申请号：US493568
申请日：1990-03-14
申请人： Robert W. Anderson , Ralph L. Gee , Trung L. Nguyen , Martin A. Hassner
发明人： Robert W. Anderson , Ralph L. Gee , Trung L. Nguyen , Martin A. Hassner
IPC分类号： G06F7/52 , G06F7/53 , G06F7/535 , G06F7/72 , G06F17/10 , H03M13/15
CPC分类号： G06F7/726 , H03M13/15
摘要： A bit-serial division method for computing the value v/u, where v and u are each n-bit vectors that are elements in a finite Galois field GF(2.sup.n) consisting of 2.sup.n elements. The n-bit components of each element in the field are coordinates of the element in a canonical basis of the field. Vector u is converted from canonical basis to a dual basis. Vector u in dual basis also comprises n bits in the finite field ordered according to an index i that takes on values from 0 to (n-1). All bits n of the converted vector u are loaded into a shift register in parallel, then converted from dual basis back to canonical basis to produce a single bit output w.sub.0 from a lookup table which generates bitwise the inverse of the n-bit vector u. The bits in the shift register are shifted (n-1) times to generate successive additional single bit outputs w.sub.i with said lookup table. Then each bit w.sub.i is multiplied by the vector v and a corresponding element c.sub.i in dual basis to generate a cumulative sum of these products that provides, upon completion of the (n-1) shifts, the bit-serial division result v/u.

2. 发明授权

US4833679A Method and apparatus with improved error correction and error information availability 失效
标题翻译：具有改进的纠错和错误信息可用性的方法和装置
公开(公告)号：US4833679A
公开(公告)日：1989-05-23
申请号：US91482
申请日：1987-08-31
申请人： Robert W. Anderson , Ralph L. Gee , Jasper A. Indelicato , Arvind M. Patel
发明人： Robert W. Anderson , Ralph L. Gee , Jasper A. Indelicato , Arvind M. Patel
IPC分类号： H03M13/00 , G11B20/12 , G11B20/18
CPC分类号： G11B20/1252 , G11B20/1809 , G11B2020/1257 , G11B2220/20
摘要： A method and apparatus is disclosed that is selectively conditionable, during read processing, to operate in normal or diagnostic on-the-fly mode or in normal or diagnostic deferred mode to correct errors in encoded uncorrected data in a disk storage device. During deferred mode operation, hardware in the disk storage device receives uncorrected data in real time and generates syndrome bytes which are decoded at the device into error pattern and error location information that is transmitted to a storage director. Circuitry is provided for retaining, if desired, error pattern and location information to facilitate identification of surface defects in the storage disk whether read processing was done on-the-fly or in deferred mode.

3. 发明授权

US4929918A Setting and dynamically adjusting VCO free-running frequency at system level 失效
标题翻译：在系统级设置和动态调整VCO自由运行频率
公开(公告)号：US4929918A
公开(公告)日：1990-05-29
申请号：US363566
申请日：1989-06-07
申请人： Paul W. Chung , Ralph L. Gee , Luke C. K. Lang , Paik Saber
发明人： Paul W. Chung , Ralph L. Gee , Luke C. K. Lang , Paik Saber
IPC分类号： G11B20/14 , G11B20/12 , H03L7/113 , H03L7/14
CPC分类号： H03L7/113 , G11B20/1258
摘要： A method and means for setting the free-running frequency of a voltage controlled oscillator (VCO) without requiring laser trimming or the like is described. The VCO forms part of an interconnected phase-locked loop (PLL) and frequency-locked loop (FLL). At system power on, the PLL is automatically disabled and a digital-to-analog (DAC) in the PLL is set to a value corresponding substantially to the center of a preselected lock range. The FLL, which includes a second DAC, then operates to generate a bias voltage for incrementing or decrementing the VCO output frequency until the VCO pulse count stored in a register equals an expected count; whereupon the VCO will be set at its free-running frequency. When the PLL is enabled, a phase error generator generates a digital phase error signal from the input data. A digital integrator converts the phase error signal to a digital frequency error signal. These error signals are added and the result is supplied to the DAC in the PLL for providing an analog output indicative of PLL frequency error. The outputs from both DACs are summed and the resultant current is converted to a bias voltage to adjust the VCO frequency as necessary for normally maintaining it within said lock range. If the VCO frequency deviates from said range, the frequency error signal to the PLL DAC is zeroed, and the frequency error signal is supplied to the FLL DAC. The phase error signal from the PLL DAC and the signal from the FLL DAC as modified by the frequency error signal are summed, and the resultant current in converted to a bias voltage to adjust the VCO frequency to within said lock range.

4. 发明授权

US5117385A Table lookup multiplier with digital filter 失效
标题翻译：表查找乘数与数字滤波器
公开(公告)号：US5117385A
公开(公告)日：1992-05-26
申请号：US772117
申请日：1991-10-08
申请人： Ralph L. Gee
发明人： Ralph L. Gee
IPC分类号： G06F1/035 , G06F7/52
CPC分类号： G06F7/5324 , G06F1/0356
摘要： In a digital multiplier for multiplying two multi-bit binary operands to produce a binary result by means of a lookup table containing all possible products of said operands, reduction of the total amount of memory required to store the table is obtained by segmenting one operand into a plurality of non-overlapping bit groups and constructing lookup tables for the bit groups, in which each lookup table contains products of its associated bit group and the other, non-partitioned operand. Multiplication is accomplished by generating partial products from the lookup tables, shifting the partial products to account for the relative significance of their associated bit groups, and adding the partial products to provide the resultant product.
摘要翻译：在用于将两个多位二进制操作数相乘以通过包含所述操作数的所有可能乘积的查找表产生二进制结果的数字乘法器中，通过将一个操作数分割成一个操作数来获得存储表所需的总存储量的减少多个非重叠比特组并且构建用于比特组的查找表，其中每个查找表包含其关联比特组的产品和另一个非分区操作数。通过从查找表中生成部分乘积，将部分乘积转换为考虑其相关位组的相对重要性，并添加部分乘积以提供最终产品来实现乘法。

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