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1. 发明授权

US4929918A Setting and dynamically adjusting VCO free-running frequency at system level 失效
标题翻译：在系统级设置和动态调整VCO自由运行频率
公开(公告)号：US4929918A
公开(公告)日：1990-05-29
申请号：US363566
申请日：1989-06-07
申请人： Paul W. Chung , Ralph L. Gee , Luke C. K. Lang , Paik Saber
发明人： Paul W. Chung , Ralph L. Gee , Luke C. K. Lang , Paik Saber
IPC分类号： G11B20/14 , G11B20/12 , H03L7/113 , H03L7/14
CPC分类号： H03L7/113 , G11B20/1258
摘要： A method and means for setting the free-running frequency of a voltage controlled oscillator (VCO) without requiring laser trimming or the like is described. The VCO forms part of an interconnected phase-locked loop (PLL) and frequency-locked loop (FLL). At system power on, the PLL is automatically disabled and a digital-to-analog (DAC) in the PLL is set to a value corresponding substantially to the center of a preselected lock range. The FLL, which includes a second DAC, then operates to generate a bias voltage for incrementing or decrementing the VCO output frequency until the VCO pulse count stored in a register equals an expected count; whereupon the VCO will be set at its free-running frequency. When the PLL is enabled, a phase error generator generates a digital phase error signal from the input data. A digital integrator converts the phase error signal to a digital frequency error signal. These error signals are added and the result is supplied to the DAC in the PLL for providing an analog output indicative of PLL frequency error. The outputs from both DACs are summed and the resultant current is converted to a bias voltage to adjust the VCO frequency as necessary for normally maintaining it within said lock range. If the VCO frequency deviates from said range, the frequency error signal to the PLL DAC is zeroed, and the frequency error signal is supplied to the FLL DAC. The phase error signal from the PLL DAC and the signal from the FLL DAC as modified by the frequency error signal are summed, and the resultant current in converted to a bias voltage to adjust the VCO frequency to within said lock range.

2. 发明授权

US4812784A Temperature stable voltage controlled oscillator with super linear wide frequency range 失效
标题翻译：具有超线性宽频率范围的温度稳定的压控振荡器
公开(公告)号：US4812784A
公开(公告)日：1989-03-14
申请号：US123024
申请日：1987-11-19
申请人： Paul W. Chung , Paik Saber
发明人： Paul W. Chung , Paik Saber
IPC分类号： H03K3/011 , H03K3/282 , H03K3/281
CPC分类号： H03K3/2821 , H03K3/011
摘要： A voltage controlled oscillator (VCO) having high temperature stability and wide voltage/frequency linearity is provided. The VCO comprises a multivibrator being switched by a bipolar type device, and temperature fluctuations of the bipolar type means are compensated by a FET current source coupled thereto. To provide a linear relationship of frequency vs. voltage over wide voltage range, the bipolar device is further regulated by a plurality of resistor and diode networks.

3. 发明授权

US5057785A Method and circuitry to suppress additive disturbances in data channels 失效
标题翻译：在数据通道中抑制加性干扰的方法和电路
公开(公告)号：US5057785A
公开(公告)日：1991-10-15
申请号：US468526
申请日：1990-01-23
申请人： Paul W. Chung , Michael O. Jenkins , Stephen A. Jove , Klaas B. Klaassen , Paik Saber , Jacobus C. L. van Peppen
发明人： Paul W. Chung , Michael O. Jenkins , Stephen A. Jove , Klaas B. Klaassen , Paik Saber , Jacobus C. L. van Peppen
IPC分类号： G11B5/09 , G11B5/00 , G11B5/012 , G11B5/02 , G11B20/02 , G11B20/24
CPC分类号： G11B20/02 , G11B20/24 , G11B5/012 , G11B2005/0016 , G11B5/02
摘要： A method and circuitry for suppressing additive transient disturbances in an analog differential input signal, such disturbances being due, for example, to thermal asperity transients caused by an MR transducer contacting a moving storage surface. The input data signal is algebraically summed with a corrective feedback signal for providing as output signal. The output signal is fed back to a circuit including an envelope detector and differentiator and converted into another signal that is the derivative of an amplitude envelope corresponding to the output signal. Nonlinear signal-adaptive filter means converts said other signal into the corrective feedback signal, which substantially replicates the additive transient disturbance and is subtracted from the data input signal to render the output signal substantially free of the transient disturbance.The input, output and corrective signals are preferably differential signals.

4. 发明授权

US5001482A BiCMOS digital-to-analog converter for disk drive digital recording channel architecture 失效
标题翻译： BiCMOS数模转换器用于磁盘驱动器数字录音通道架构
公开(公告)号：US5001482A
公开(公告)日：1991-03-19
申请号：US536431
申请日：1990-06-11
申请人： Paul W. S. Chung , David S. Lowrie , Paik Saber , Chorng K. Wang
发明人： Paul W. S. Chung , David S. Lowrie , Paik Saber , Chorng K. Wang
IPC分类号： G05F3/26 , G11B20/10 , G11B20/14 , H03L7/085 , H03M1/06 , H03M1/66 , H03M1/74
CPC分类号： H03M1/0619 , G05F3/262 , G11B20/10 , G11B20/10055 , G11B20/1403 , H03L7/085 , H03M1/747
摘要： A digital-to-analog converter for use in a timing control loop. The converter includes a plurality of cells, each activated in response to a timing loop control signal. The converter also includes a resistive current mirror, with a first resistance R1, providing a reference curent which is mirrored in each cell by a current source FET. Each cell is constructed to switch the current from its current source FET through an output FET when a respective control bit provided to the cell is positive. Otherwise, the current is diverted through a sink FET. All of the cell output FETs are tied to a single resistance R2 which collects the currents of the active cells and provides the AC output of the converter. The converter's output is related only to the ratio R2/R1, thereby decoupling process, temperature, and voltage effects from the output of the converter.

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