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1. 发明授权

US07471645B2 Method and system for multicast in a broadband satellite system 有权
标题翻译：宽带卫星系统中组播的方法和系统
公开(公告)号：US07471645B2
公开(公告)日：2008-12-30
申请号：US10684914
申请日：2003-10-14
申请人： Robert Torres , Thomas Fletcher , Robert Aryee , Mangala Kannan
发明人： Robert Torres , Thomas Fletcher , Robert Aryee , Mangala Kannan
IPC分类号： H04L12/28 , H04J3/26
CPC分类号： H04B7/18595
摘要： An approach is provided for adapting multicast services originating from a terrestrial network over a satellite network. A request for establishing a multicast session corresponding to a network address of the terrestrial network is received at a hub station. The request specifies participating satellite terminals in the multicast session. The hub station assigns an address unique within the satellite network to map to the network address for the multicast session. The participating satellite terminals are configured with the assigned satellite address. A distribution mechanism is selected to transport dataflow of the multicast session to the participating satellite terminals. The distribution mechanism utilizes one or more spot beams covering the participating satellite terminals, wherein the selected distribution mechanism is switched to another one of the distribution mechanisms based on capacity of the satellite network and reachability of the participating satellite terminals.
摘要翻译：提供了一种用于通过卫星网络适配来自地面网络的多播服务的方法。在中心站接收到建立与地面网络的网络地址相对应的多播会话的请求。该请求指定多播会话中的参与卫星终端。中心站在卫星网络内分配唯一的地址以映射到组播会话的网络地址。参与的卫星终端配置有分配的卫星地址。选择分配机制将组播会话的数据流传输到参与的卫星终端。分配机制利用覆盖参与卫星终端的一个或多个点波束，其中基于卫星网络的容量和参与的卫星终端的可达性，选择的分配机制被切换到另一个分配机制。

2. 发明申请

US20070226739A1 Process scheduler employing adaptive partitioning of process threads 有权
标题翻译：进程调度程序使用进程线程的自适应分区
公开(公告)号：US20070226739A1
公开(公告)日：2007-09-27
申请号：US11317468
申请日：2005-12-22
申请人： Dan Dodge , Attila Danko , Sebastien Marineau-Mes , Peter Veen , Colin Burgess , Thomas Fletcher , Brian Stecher
发明人： Dan Dodge , Attila Danko , Sebastien Marineau-Mes , Peter Veen , Colin Burgess , Thomas Fletcher , Brian Stecher
IPC分类号： G06F9/46
CPC分类号： G06F9/5038 , G06F9/4881 , G06F9/4887 , G06F9/505 , G06F9/5077
摘要： A system is set forth that comprises a processor, such as a single processor or symmetric multiprocessor, and one or more memory storage units. The system also includes software code that is stored in the memory storage units. The software code is executable by the processor and comprises code for generating a plurality of adaptive partitions that are each associated with one or more software threads. Each of the adaptive partitions has a corresponding processor budget. The code also is executable to generate at least one sending thread and at least one receiving thread. The receiving thread responds to communications from the sending thread to execute one or more tasks corresponding to the communications. A scheduling system also forms at least part of the code that is executable by the processor. In operation, the scheduling system selectively allocates the processor to each sending and receiving thread based, at least in part, on the processor budget of the adaptive partition associated with the respective thread. In this type of sending/receiving environment, the scheduling system bills the processor budget of the adaptive partition associated with the sending thread for processor allocation used by the receiving thread to respond to communications sent by the sending thread.
摘要翻译：提出了一种包括诸如单个处理器或对称多处理器的处理器以及一个或多个存储器存储单元的系统。该系统还包括存储在存储器单元中的软件代码。软件代码可由处理器执行，并且包括用于生成与一个或多个软件线程相关联的多个自适应分区的代码。每个自适应分区具有相应的处理器预算。代码也是可执行的，以生成至少一个发送线程和至少一个接收线程。接收线程响应来自发送线程的通信，以执行与通信相对应的一个或多个任务。调度系统还形成可由处理器执行的代码的至少一部分。在操作中，调度系统至少部分地基于与相应线程相关联的自适应分区的处理器预算来选择性地将处理器分配给每个发送和接收线程。在这种发送/接收环境中，调度系统对与发送线程相关联的自适应分区的处理器预算进行计费，以便接收线程使用的处理器分配来响应发送线程发送的通信。

3. 发明申请

US20060241719A1 Electrical stimulation of tissue for therapeutic and diagnostic purposes 失效
公开(公告)号：US20060241719A1
公开(公告)日：2006-10-26
申请号：US11473563
申请日：2006-06-23
申请人： George Foster , Thomas Fletcher
发明人： George Foster , Thomas Fletcher
IPC分类号： A61N1/32
CPC分类号： A61N1/32 , A61N1/08 , A61N1/40
摘要： Electrobiological stimulation is carried out transcranially by applying high frequency squarewave bursts exhibiting no d.c. term across the cranial region. Such stimulation is commenced employing ramp generators and positive and negative voltage converters which evolve the requisite baseform and burst frequencies having a voltage waveform which is square in nature. Both voltage and current are sensed and subjected to comparator logic in conjunction with predetermined thresholds and windows. Overcurrent detection and overvoltage detection is provided in hard wired fashion to assure rapid shutdown response. D.C offset detection is provided along with waveform balance tests to further assure the safety of the system. Diagnostic procedures as well as therapeutic procedures may be carried out with a system version which provides for the application of a stimulus in conjunction with safety monitoring and controller based development of stimulating waveforms, all of which exhibits no d.c. term. Feed point voltage waveforms and current waveforms are mathematically processed and compared for diagnostic analysis.

4. 发明申请

US20060206881A1 Process scheduler employing adaptive partitioning of critical process threads 有权
标题翻译：进程调度程序使用关键进程线程的自适应分区
公开(公告)号：US20060206881A1
公开(公告)日：2006-09-14
申请号：US11371638
申请日：2006-03-08
申请人： Dan Dodge , Attilla Danko , Sebastien Marineau-Mes , Peter van der Veen , Colin Burgess , Thomas Fletcher , Brian Stecher
发明人： Dan Dodge , Attilla Danko , Sebastien Marineau-Mes , Peter van der Veen , Colin Burgess , Thomas Fletcher , Brian Stecher
IPC分类号： G06F9/45
CPC分类号： G06F9/4881
摘要： A system is set forth that includes a processor, one or more memory storage units, and software code stored in the one or more memory storage units. The software code is executable by the processor to generate a plurality of adaptive partitions that are each associated with one or more process threads. Each of the plurality of adaptive partitions has a corresponding processor time budget. One or more of the process threads are designated as critical threads. Each adaptive partition associated with a critical thread is assigned a corresponding critical time budget. The software code also includes a scheduling system that is executable by the processor for selectively allocating the processor to run the process threads based, at least in part, on the processor time budgets of the respective adaptive partitions. The scheduling system may allocate the processor to run a critical thread based on the available critical time budget of the associated adaptive partition even when the processor time budget of the associated adaptive partition has been exhausted. In one example, the scheduling system functions SO that it only bills the critical time budget of an adaptive partition for time used to run an associated critical thread when the processor is overloaded and the critical time budget for the adaptive partition is concurrently exhausted. Methods of implementing such a system are also set forth.
摘要翻译：提出了一种包括处理器，一个或多个存储器单元和存储在一个或多个存储器存储单元中的软件代码的系统。软件代码可由处理器执行以产生多个与一个或多个进程线程相关联的自适应分区。多个自适应分区中的每一个具有对应的处理器时间预算。一个或多个进程线程被指定为关键线程。与关键线程相关联的每个自适应分区都被分配相应的关键时间预算。软件代码还包括调度系统，其可由处理器执行，用于至少部分地基于相应自适应分区的处理器时间预算来选择性地分配处理器来运行处理线程。即使相关联的自适应分区的处理器时间预算已经耗尽，调度系统也可以基于相关自适应分区的可用关键时间预算来分配处理器来运行关键线程。在一个示例中，调度系统的功能是，当处理器过载时，它仅对用于运行相关联的关键线程的时间用于自适应分区的关键时间预算并且同时耗尽自适应分区的关键时间预算。还阐述了实现这种系统的方法。

5. 发明申请

US20110107342A1 PROCESS SCHEDULER EMPLOYING ORDERING FUNCTION TO SCHEDULE THREADS RUNNING IN MULTIPLE ADAPTIVE PARTITIONS 有权
标题翻译：流程调度员在多个自适应分段中执行计划螺线管理功能
公开(公告)号：US20110107342A1
公开(公告)日：2011-05-05
申请号：US12978083
申请日：2010-12-23
申请人： Dan Dodge , Attilla Danko , Sebastien Marineau-Mes , Peter van der Veen , Colin Burgess , Thomas Fletcher , Brian Stecher
发明人： Dan Dodge , Attilla Danko , Sebastien Marineau-Mes , Peter van der Veen , Colin Burgess , Thomas Fletcher , Brian Stecher
IPC分类号： G06F9/46
CPC分类号： G06F9/4881
摘要： A system is set forth that includes a processor, one or more memory storage units, and software code stored in the one or more memory storage units. The software code is executable by the processor to generate a plurality of adaptive partitions that are each associated with one or more process threads. Each of the plurality, of adaptive partitions has one or more corresponding scheduling attributes that are assigned to it. The software code further includes a scheduling system that is executable by the processor for selectively allocating the processor to run the process threads based on a comparison between ordering function values for each adaptive partition. The ordering function value for each adaptive partition is calculated using one or more of the scheduling attributes of the corresponding adaptive partition. The scheduling attributes that may be used to calculate the ordering function value include, for example, 1) the process budget, such as a guaranteed time budget, of the adaptive partition, 2) the critical budget, if any, of the adaptive partition, 3) the rate at which the process threads of an adaptive partition consume processor time, or the like. For each adaptive partition that is associated with a critical thread, a critical ordering function value also may be calculated. The scheduling system may compare the ordering function value with the critical ordering function value of the adaptive partition to determine the proper manner of billing the adaptive partition for the processor allocation used to run its associated critical threads. Methods of implementing various aspects of such a system are also set forth.
摘要翻译：提出了一种包括处理器，一个或多个存储器单元和存储在一个或多个存储器存储单元中的软件代码的系统。软件代码可由处理器执行以产生多个与一个或多个进程线程相关联的自适应分区。多个自适应分区中的每一个具有分配给它的一个或多个对应的调度属性。软件代码还包括可由处理器执行的调度系统，用于基于每个自适应分区的排序函数值之间的比较来选择性地分配处理器来运行处理线程。使用相应自适应分区的一个或多个调度属性来计算每个自适应分区的排序函数值。可用于计算排序函数值的调度属性包括例如1）自适应分区的过程预算，例如保证时间预算，2）自适应分区的关键预算（如果有的话） 3）自适应分区的进程线程消耗处理器时间的速率等。对于与关键线程相关联的每个自适应分区，也可以计算临界排序函数值。调度系统可以将排序函数值与自适应分区的关键排序函数值进行比较，以确定用于运行其关联关键线程的处理器分配的自适应分区计费的适当方式。还阐述了实现这种系统的各个方面的方法。

6. 发明申请

US20070061809A1 Process scheduler having multiple adaptive partitions associated with process threads accessing mutexes and the like 有权
标题翻译：具有与进程线程相关联的多个自适应分区的进程调度器访问互斥等
公开(公告)号：US20070061809A1
公开(公告)日：2007-03-15
申请号：US11371639
申请日：2006-03-08
申请人： Dan Dodge , Attilla Danko , Sebastien Marineau-Mes , Peter Veen , Colin Burgess , Thomas Fletcher , Brian Stecher
发明人： Dan Dodge , Attilla Danko , Sebastien Marineau-Mes , Peter Veen , Colin Burgess , Thomas Fletcher , Brian Stecher
IPC分类号： G06F9/46
CPC分类号： G06F9/4881
摘要： A system is set forth that includes a processor, one or more memory storage units, and software code stored in the one or more memory storage units. The software code is executable by the processor to generate a plurality of adaptive partitions that are each associated with one or more process threads. Each of the plurality of adaptive partitions has a corresponding processor budget that is assigned to it. The process threads include a mutex holding thread and a mutex waiting thread. The mutex holding thread is associated with a first adaptive partition and may gain exclusive access to a mutex object. The mutex waiting thread is associated with a second adaptive partition and must wait for access to the mutex object while the mutex object is held by the mutex holding thread. The software code further includes a scheduling system that selectively allocates the processor to run the process threads based, at least in part, on the processor budget of the associated adaptive partitions. The scheduling system bills processor allocation used to run the mutex holding thread to the processor budget of the second adaptive partition when the processor budget of the first adaptive partition has been exhausted.
摘要翻译：提出了一种包括处理器，一个或多个存储器单元和存储在一个或多个存储器存储单元中的软件代码的系统。软件代码可由处理器执行以产生多个与一个或多个进程线程相关联的自适应分区。多个自适应分区中的每一个具有分配给它的对应的处理器预算。进程线程包括互斥锁持线程和互斥等待线程。互斥保持线程与第一自适应分区相关联，并且可以获得对互斥体对象的独占访问。互斥等待线程与第二自适应分区相关联，并且必须等待互斥对象的访问，而互斥体对象由互斥锁持线程保持。软件代码还包括调度系统，其至少部分地基于相关联的自适应分区的处理器预算来选择性地分配处理器来运行处理线程。当第一自适应分区的处理器预算已经用尽时，调度系统将处理器分配用于将互斥保持线程运行到第二自适应分区的处理器预算。

7. 发明授权

US09323500B2 Reducing power consumption in a fused multiply-add (FMA) unit responsive to input data values 有权
公开(公告)号：US09323500B2
公开(公告)日：2016-04-26
申请号：US13785528
申请日：2013-03-05
申请人： Brian Hickmann , Dennis Bradford , Thomas Fletcher
发明人： Brian Hickmann , Dennis Bradford , Thomas Fletcher
IPC分类号： G06F7/38 , G06F7/60 , G06F7/48 , G06F7/57 , G06F7/483 , G06F7/544 , G06F9/30 , G06F1/32
CPC分类号： G06F7/60 , G06F1/324 , G06F1/3243 , G06F7/48 , G06F7/483 , G06F7/5443 , G06F7/57 , G06F9/30 , G06F9/3001 , G06F2207/3884 , Y02D10/126 , Y02D10/152
摘要： In an embodiment, a fused multiply-add (FMA) circuit is configured to receive a plurality of input data values to perform an FMA instruction on the input data values. The circuit includes a multiplier unit and an adder unit coupled to an output of the multiplier unit, and a control logic to receive the input data values and to reduce switching activity and thus reduce power consumption of one or more components of the circuit based on a value of one or more of the input data values. Other embodiments are described and claimed.

8. 发明申请

US20150370636A1 CONSECUTIVE BIT ERROR DETECTION AND CORRECTION 有权
标题翻译：协调位错误检测和修正
公开(公告)号：US20150370636A1
公开(公告)日：2015-12-24
申请号：US14308107
申请日：2014-06-18
申请人： Guillem Sole , Roger Espasa , Sorin Iacobovici , Brian Hickmann , Wei Wu , Thomas Fletcher
发明人： Guillem Sole , Roger Espasa , Sorin Iacobovici , Brian Hickmann , Wei Wu , Thomas Fletcher
IPC分类号： G06F11/10 , H03M13/00
CPC分类号： H03M13/09 , G06F11/1012 , H03M13/17 , H03M13/19 , H03M13/29
摘要： Embodiments of an invention for consecutive bit error detection and correction are disclosed. In one embodiment, an apparatus includes a storage structure, a second storage structure, a parity checker, an error correction code (ECC) checker, and an error corrector. The first storage structure is to store a plurality of data values, a plurality of parity values, and a plurality of ECC values, each parity value corresponding to one of the plurality of data values, a first bit of each parity value corresponding to a first of a plurality of portions of a corresponding data value, wherein the first of the plurality of portions of the corresponding data value is interleaved with a second of the plurality of portions of the corresponding data value, wherein a second bit of each parity value corresponds to a second of the plurality of portions of the corresponding data value, each ECC value corresponding to one of the plurality of data values. The parity checker is to detect a parity error in a data value stored in the first storage structure using a parity value corresponding to the data value. The ECC checker is to generate a syndrome. The error corrector is to detect and correct consecutive bit errors in the data value using the syndrome.
摘要翻译：公开了用于连续位错检测和校正的发明的实施例。在一个实施例中，一种装置包括存储结构，第二存储结构，奇偶校验器，纠错码（ECC）检查器和纠错器。第一存储结构是存储多个数据值，多个奇偶校验值和多个ECC值，每个奇偶校验值对应于多个数据值之一，每个奇偶校验值的第一位对应于第一对应数据值的多个部分中的相应数据值的多个部分中的第一部分与相应数据值的多个部分中的第二部分进行交织，其中每个奇偶校验值的第二位对应于相应数据值的多个部分中的第二个，每个ECC值对应于多个数据值之一。奇偶校验器使用与数据值相对应的奇偶校验值来检测存储在第一存储结构中的数据值中的奇偶校验错误。 ECC检查器是产生综合征。错误校正器是使用综合征来检测和纠正数据值中的连续位错误。

9. 发明授权

US07870554B2 Process scheduler employing ordering function to schedule threads running in multiple adaptive partitions 有权
标题翻译：进程调度器采用排序函数来调度在多个自适应分区中运行的线程
公开(公告)号：US07870554B2
公开(公告)日：2011-01-11
申请号：US11371634
申请日：2006-03-08
申请人： Dan Dodge , Attilla Danko , Sebastien Marineau-Mes , Peter van der Veen , Colin Burgess , Thomas Fletcher , Brian Stecher
发明人： Dan Dodge , Attilla Danko , Sebastien Marineau-Mes , Peter van der Veen , Colin Burgess , Thomas Fletcher , Brian Stecher
IPC分类号： G06F9/46
CPC分类号： G06F9/4881
摘要： A system includes a processor, one or more memory storage units, and software code stored in the memory storage units. The software code is executable by the processor to generate a plurality of adaptive partitions that are each associated with one or more process threads. Each of adaptive partition has one or more corresponding assigned scheduling attributes. The software code includes a scheduling system for selectively allocating the processor to run process threads based on a comparison between ordering function values for each adaptive partition. Ordering function values are calculated based on scheduling attributes of the corresponding adaptive partition. A critical ordering function value also may be calculated and used to determine the proper manner of billing an associated adaptive partition for the processor allocation used to run its associated critical threads. Methods of implementing various aspects of such a system are also set forth.
摘要翻译：系统包括处理器，一个或多个存储器单元和存储在存储器存储单元中的软件代码。软件代码可由处理器执行以产生多个与一个或多个进程线程相关联的自适应分区。每个自适应分区具有一个或多个相应的分配的调度属性。该软件代码包括一个调度系统，用于基于每个自适应分区的排序函数值之间的比较来选择性地分配处理器来运行处理线程。根据相应自适应分区的调度属性计算订购功能值。关键排序函数值也可以被计算并用于确定用于运行其相关联的关键线程的处理器分配的相关自适应分区的适当的计费方式。还阐述了实现这种系统的各个方面的方法。

10. 发明申请

US20070061788A1 Process scheduler employing ordering function to schedule threads running in multiple adaptive partitions 有权
标题翻译：进程调度器采用排序函数来调度在多个自适应分区中运行的线程
公开(公告)号：US20070061788A1
公开(公告)日：2007-03-15
申请号：US11371634
申请日：2006-03-08
申请人： Dan Dodge , Attilla Danko , Sebastien Marineau-Mes , Peter Veen , Colin Burgess , Thomas Fletcher , Brian Stecher
发明人： Dan Dodge , Attilla Danko , Sebastien Marineau-Mes , Peter Veen , Colin Burgess , Thomas Fletcher , Brian Stecher
IPC分类号： G06F9/45
CPC分类号： G06F9/4881
摘要： A system is set forth that includes a processor, one or more memory storage units, and software code stored in the one or more memory storage units. The software code is executable by the processor to generate a plurality of adaptive partitions that are each associated with one or more process threads. Each of the plurality of adaptive partitions has one or more corresponding scheduling attributes that are assigned to it. The software code further includes a scheduling system that is executable by the processor for selectively allocating the processor to run the process threads based on a comparison between ordering function values for each adaptive partition. The ordering function value for each adaptive partition is calculated using one or more of the scheduling attributes of the corresponding adaptive partition. The scheduling attributes that may be used to calculate the ordering function value include, for example, 1) the process budget, such as a guaranteed time budget, of the adaptive partition, 2) the critical budget, if any, of the adaptive partition, 3) the rate at which the process threads of an adaptive partition consume processor time, or the like. For each adaptive partition that is associated with a critical thread, a critical ordering function value also may be calculated. The scheduling system may compare the ordering function value with the critical ordering function value of the adaptive partition to determine the proper manner of billing the adaptive partition for the processor allocation used to run its associated critical threads. Methods of implementing various aspects of such a system are also set forth.
摘要翻译：提出了一种包括处理器，一个或多个存储器单元和存储在一个或多个存储器存储单元中的软件代码的系统。软件代码可由处理器执行以产生多个与一个或多个进程线程相关联的自适应分区。多个自适应分区中的每一个具有分配给它的一个或多个对应的调度属性。软件代码还包括可由处理器执行的调度系统，用于基于每个自适应分区的排序函数值之间的比较来选择性地分配处理器来运行处理线程。使用相应自适应分区的一个或多个调度属性来计算每个自适应分区的排序函数值。可用于计算排序函数值的调度属性包括例如1）自适应分区的过程预算，例如保证时间预算，2）自适应分区的关键预算（如果有的话） 3）自适应分区的进程线程消耗处理器时间的速率等。对于与关键线程相关联的每个自适应分区，也可以计算临界排序函数值。调度系统可以将排序函数值与自适应分区的关键排序函数值进行比较，以确定用于运行其关联关键线程的处理器分配的自适应分区计费的适当方式。还阐述了实现这种系统的各个方面的方法。

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