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1. 发明授权

US6101597A Method and apparatus for maximum throughput scheduling of dependent operations in a pipelined processor 失效
标题翻译：用于流水线处理器中依赖操作的最大吞吐量调度的方法和装置
公开(公告)号：US6101597A
公开(公告)日：2000-08-08
申请号：US176370
申请日：1993-12-30
申请人： Robert P. Colwell , Michael A. Fetterman , Glenn J. Hinton , Robert W. Martell , David B. Papworth
发明人： Robert P. Colwell , Michael A. Fetterman , Glenn J. Hinton , Robert W. Martell , David B. Papworth
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3824 , G06F9/383
摘要： Maximum throughput or "back-to-back" scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the prospective determination of the availability of a source operand before the operand itself is actually computed as a result of the execution of another instruction. Storage addresses of the source operands of an instruction are stored in a content addressable memory (CAM). Before an instruction is executed and its result data written back, the storage location address of the result is provided to the CAM and associatively compared with the source operand addresses stored therein. A CAM match and its accompanying match bit indicate that the result of the instruction to be executed will provide a source operand to the dependent instruction waiting in the reservation station. Using a bypass mechanism, if the operand is computed after dispatch of the dependent instruction, then the source operand is provided directly from the execution unit computing the source operand to a source operand input of the execution unit executing the dependent instruction.
摘要翻译：通过最大化处理器确定依赖指令的源操作数的可用性的效率，并将这些操作数提供给执行依赖的执行单元，从而实现流水线处理器中相关指令的最大吞吐量或“背对背” 指令。这两个操作通过多个机制来实现。用于确定源操作数的可用性以及因此用于发送到可用执行单元的依赖指令的准备的机制依赖于在操作数本身实际计算之前源操作数的可用性的预期确定执行另一条指令。指令的源操作数的存储地址存储在内容可寻址存储器（CAM）中。在执行指令并且其结果数据被写回之前，将结果的存储位置地址提供给CAM并与存储在其中的源操作数地址相关联地进行比较。 CAM匹配及其伴随的匹配位指示要执行的指令的结果将为在保留站等待的从属指令提供源操作数。使用旁路机制，如果在分派依赖指令之后计算操作数，则将操作数从执行单元直接提供到计算源操作数到执行依赖指令的执行单元的源操作数输入。

2. 发明授权

US5604878A Method and apparatus for avoiding writeback conflicts between execution units sharing a common writeback path 失效
标题翻译：避免共享共同回写路径的执行单元之间的回写冲突的方法和装置
公开(公告)号：US5604878A
公开(公告)日：1997-02-18
申请号：US513679
申请日：1995-08-01
申请人： Robert P. Colwell , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , Robert W. Martell , David B. Papworth
发明人： Robert P. Colwell , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , Robert W. Martell , David B. Papworth
IPC分类号： G06F9/38 , G06F13/00
CPC分类号： G06F9/3873 , G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3867
摘要： Pipeline lengthening in functional units likely to be involved in a writeback conflict is implemented to avoid conflicts. Logic circuitry is provided for comparing the depths of two concurrently executing execution unit pipelines to determine if a conflict will develop. When it appears that two execution units will attempt to write back at the same time, the execution unit having a shorter pipeline will be instructed to add a stage to its pipeline, storing its result in a delaying buffer for one clock cycle. After the conflict has been resolved, the instruction to lengthen the pipeline of a given functional unit will be rescinded. Multistage execution units are designed to signal a reservation station to delay the dispatch of various instructions to avoid conflicts between execution units.
摘要翻译：执行可能参与回写冲突的功能单位的管道延长，以避免冲突。提供逻辑电路用于比较两个并发执行的执行单元管线的深度，以确定冲突是否会发展。当看来两个执行单元将尝试同时回写时，将指示具有较短流水线的执行单元向其流水线添加一个阶段，将其结果存储在一个时钟周期的延迟缓冲器中。冲突解决后，延长给定功能单位管道的指示将被撤销。多级执行单元被设计为用信号通知保留站来延迟各种指令的发送以避免执行单元之间的冲突。

3. 发明授权

US5546597A Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution 失效
标题翻译：在执行无序指令执行的处理器中，使用多周期凸轮准备选择依赖于数据的指令
公开(公告)号：US5546597A
公开(公告)日：1996-08-13
申请号：US203050
申请日：1994-02-28
申请人： Robert W. Martell , Glenn J. Hinton , Michael A. Fetterman , David B. Papworth , Robert P. Colwell , Andrew F. Glew
发明人： Robert W. Martell , Glenn J. Hinton , Michael A. Fetterman , David B. Papworth , Robert P. Colwell , Andrew F. Glew
IPC分类号： G06F9/38 , G06F9/345
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： An instruction dispatch circuit is disclosed that improves instruction execution throughput for a processor. The instruction dispatch circuit comprises an instruction buffer with a plurality of instruction entries and a content addressable memory array having at least one cam entry corresponding to each instruction entry. Each cam entry stores at least one source tag for the corresponding instruction entry. The content addressable memory array matches to a result tag from an execution circuit over a result bus, wherein the execution circuit transfers the result tag over the result bus at least one clock cycle before transferring a corresponding result data value over the result bus. Each cam entry generates a cam match signal used to determine whether data dependent instruction are ready for dispatch.
摘要翻译：公开了一种提高处理器的指令执行吞吐量的指令调度电路。指令调度电路包括具有多个指令条目的指令缓冲器和具有对应于每个指令条目的至少一个凸轮条目的内容可寻址存储器阵列。每个凸轮条目存储用于相应指令条目的至少一个源标签。内容可寻址存储器阵列通过结果总线与来自执行电路的结果标签相匹配，其中执行电路在通过结果总线传送相应的结果数据值之前至少一个时钟周期在结果总线上传送结果标签。每个凸轮条目产生一个凸轮匹配信号，用于确定数据相关指令是否准备好进行发送。

4. 发明授权

US5987600A Exception handling in a processor that performs speculative out-of-order instruction execution 失效
标题翻译：处理器中执行异常指令执行的异常处理
公开(公告)号：US5987600A
公开(公告)日：1999-11-16
申请号：US851140
申请日：1997-05-05
申请人： David B. Papworth , Glenn J. Hinton , Michael A. Fetterman , Robert P. Colwell , Andrew F. Glew
发明人： David B. Papworth , Glenn J. Hinton , Michael A. Fetterman , Robert P. Colwell , Andrew F. Glew
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3865 , G06F9/3842 , G06F9/3863
摘要： A method and circuitry for coordinating exceptions in a processor. The processor generates a result data value and an exception data value for each instruction wherein the exception data value specifies whether the corresponding instruction causes an exception. The processor commits the result data values to an architectural state of the processor in the sequential program order, and fetches an exception handler to processes the exception if the exception is indicated by one of the exception data values. The processor fetches an asynchronous event handler to processes an asynchronous event if the asynchronous event is detected while the result data values are committed to the architectural state of the processor.
摘要翻译：用于协调处理器中的异常的方法和电路。处理器为每个指令生成结果数据值和异常数据值，其中异常数据值指定相应指令是否引起异常。处理器以顺序程序顺序将结果数据值提交给处理器的架构状态，并且如果异常由异常数据值之一指示，则提取异常处理程序来处理异常。如果在结果数据值提交到处理器的架构状态时检测到异步事件，处理器将获取异步事件处理程序来处理异步事件。

5. 发明授权

US5627985A Speculative and committed resource files in an out-of-order processor 失效
标题翻译：乱序处理器中的投机和承诺资源文件
公开(公告)号：US5627985A
公开(公告)日：1997-05-06
申请号：US177244
申请日：1994-01-04
申请人： Michael A. Fetterman , Andrew F. Glew , David B. Papworth , Glenn J. Hinton , Robert P. Colwell
发明人： Michael A. Fetterman , Andrew F. Glew , David B. Papworth , Glenn J. Hinton , Robert P. Colwell
IPC分类号： G06F9/38 , G06F9/34
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A speculative execution out of order processor comprising a reorder circuit containing a plurality of physical registers that buffer speculative execution results for integer and floating-point operations, and a real register circuit containing a plurality of committed state registers that buffer committed execution results for either integer or floating-point operations, depending on the register. The reorder and real register circuits read the speculative and committed source data values for incoming micro-ops, and transfer the speculative and committed source data values over to a micro-op dispatch circuit over a common data path. A retire logic circuit commits the speculative execution results to an architectural state by transferring the speculative execution results from the reorder circuit to the real register circuit.
摘要翻译：一种推测执行乱序处理器，包括一个包含多个物理寄存器的重排序电路，该多个物理寄存器缓冲整数和浮点运算的推测执行结果，以及一个包含多个提交状态寄存器的实际寄存器电路，该寄存器电路缓冲任一整数的提交执行结果或浮点运算，具体取决于寄存器。重排序和实际寄存器电路读取输入微操作的推测和确定的源数据值，并通过公共数据路径将推测和承诺的源数据值传输到微操作调度电路。退出逻辑电路通过将推测执行结果从重新排序电路传送到实际寄存器电路来将推测执行结果提交到架构状态。

6. 发明授权

US5913050A Method and apparatus for providing address-size backward compatibility in a processor using segmented memory 失效
标题翻译：在使用分段存储器的处理器中提供地址大小向后兼容性的方法和装置
公开(公告)号：US5913050A
公开(公告)日：1999-06-15
申请号：US735048
申请日：1996-10-22
申请人： Darrell D. Boggs , Robert P. Colwell , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , David B. Papworth
发明人： Darrell D. Boggs , Robert P. Colwell , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , David B. Papworth
IPC分类号： G06F9/32 , G06F9/38 , G06F12/06 , G06F9/26
CPC分类号： G06F9/3804 , G06F9/30054
摘要： This invention overcomes the address size backward compatibility problem by first subtracting the segment base address from the linear destination address of a branch instruction to generate a virtual destination address. It is assumed that the branch instruction destination address is n bits long with m most significant bits. It is desired to provide backward compatibility in the n-bit processor for branch instruction code written for processors utilizing instruction address fields of size (n-m) bits. After obtaining the virtual address, if any of the m most significant bits are non-zero, then those m bits are set to zero to thereby generate a corrected virtual address. If such a compatibility correction is necessary, then a clear signal is asserted to flush all state of the processor that resulted from instructions being fetched after the branch instruction was fetched. The corrected virtual address is added back to the segment base address to generate a corrected linear address. The next instruction is fetched at the corrected linear address.
摘要翻译：本发明通过首先从分支指令的线性目的地地址中减去分段基地址来生成虚拟目的地地址来克服地址大小向后兼容性问题。假设分支指令目标地址是n位长，m个最高有效位。期望在n比特处理器中为使用大小（n-m）比特的指令地址字段为处理器编写的分支指令代码提供向后兼容性。在获得虚拟地址之后，如果m个最高有效位中的任何一个非零，则将这些m位设置为零，从而生成校正的虚拟地址。如果需要这种兼容性校正，则清除信号被断言以清除在分支指令被取出之后被取出的指令导致的处理器的所有状态。校正的虚拟地址被加回到段基地址以产生校正的线性地址。下一条指令是在校正的线性地址处获取的。

7. 发明授权

US5809271A Method and apparatus for changing flow of control in a processor 失效
标题翻译：改变处理器中控制流程的方法和装置
公开(公告)号：US5809271A
公开(公告)日：1998-09-15
申请号：US518563
申请日：1995-08-23
申请人： Robert P. Colwell , Atiq Bajwa , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , David B. Papworth
发明人： Robert P. Colwell , Atiq Bajwa , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , David B. Papworth
IPC分类号： G06F9/32 , G06F9/38 , G06F9/26
CPC分类号： G06F9/3865 , G06F9/322 , G06F9/3844
摘要： A simplified method and apparatus for handling the change of instruction control flow in a microprocessor is provided. Rather than attempting to implement a change in the instruction flow immediately, the processor first recognizes that flow is to be redirected from a predicted instruction flow to a correct instruction flow according to a flow control indicator. The flow control indicator may be attached to instructions flowing down the pipeline or inserted as a separate instruction in the pipeline. The pipeline is cleared of state created by instructions that do not follow the correct instruction flow, i.e., instructions that were erroneously fetched after the instruction causing the change in flow. The change in flow as indicated by the flow control indicator is implemented later in the pipeline.
摘要翻译：提供了一种用于处理微处理器中指令控制流程变化的简化方法和装置。处理器不是试图立即实现指令流程的改变，而是根据流量控制指示符首先识别流程将从预测指令流重定向到正确的指令流。流量控制指示器可以附接到沿着流水线向下流动的指令或作为管道中的单独指令插入。管道被清除由不遵循正确指令流程的指令创建的状态，即在引起流量变化的指令之后被错误地取出的指令。流量控制指示器所示的流量变化在后面的流水线中实现。

8. 发明授权

US5778245A Method and apparatus for dynamic allocation of multiple buffers in a processor 失效
标题翻译：用于在处理器中动态分配多个缓冲器的方法和装置
公开(公告)号：US5778245A
公开(公告)日：1998-07-07
申请号：US204861
申请日：1994-03-01
申请人： David B. Papworth , Andrew F. Glew , Glenn J. Hinton , Robert P. Colwell , Michael A. Fetterman , Shantanu R. Gupta , James S. Griffith
发明人： David B. Papworth , Andrew F. Glew , Glenn J. Hinton , Robert P. Colwell , Michael A. Fetterman , Shantanu R. Gupta , James S. Griffith
IPC分类号： G06F9/38 , G06F9/50 , G06F15/82
CPC分类号： G06F9/5016 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A method and apparatus for dynamically allocating entries of microprocessor resources to particular instructions in an efficient manner to efficiently utilize buffer size and resources. The pipelined and superscalar microprocessor is capable of speculatively executing instructions and also out-of-order processing. Resources within the microprocessor include a store buffer, a load buffer, a reorder buffer and a reservation station. The reorder buffer contains a larger set of physical registers and also contains information related to speculative instructions and the reservation station comprises information related to instructions pending execution. The load buffer is only allocated to load instructions and is valid for an instruction from allocation pipestage to instruction retirement. The store buffer is only allocated to store instructions and is valid for an instruction from allocation to store performance. The reservation station is allocated to most instructions and is valid for an instruction from allocation to instruction dispatch. The reorder buffer is allocated to all instructions and is valid for a given instruction from allocation to retirement. The load buffer, store buffer, and reorder buffer are sequentially allocated while the reservation station is not. Resource allocation is performed dynamically (as needed by the operation) rather than as a full set of resources attached to each operation. Using the above allocation scheme, efficient usage of the microprocessor resources is accomplished.
摘要翻译：一种用于以有效方式动态地将微处理器资源的条目分配给特定指令以有效利用缓冲器大小和资源的方法和装置。流水线和超标量微处理器能够推测性地执行指令并进行无序处理。微处理器内的资源包括存储缓冲器，加载缓冲器，重新排序缓冲器和保留站。重排序缓冲器包含较大的一组物理寄存器，并且还包含与推测指令相关的信息，并且保留站包括与待执行的指令相关的信息。加载缓冲区仅分配给加载指令，对从分配管理到指令退出的指令有效。存储缓冲区仅被分配用于存储指令，并且对于分配的指令有效以存储性能。保留站被分配给大多数指令，并且对于从分配到指令分派的指令是有效的。重新排序缓冲区被分配给所有指令，并且对于从分配到退休的给定指令是有效的。在保留站不存在的情况下顺序地分配负载缓冲器，存储缓冲器和重排序缓冲器。动态执行资源分配（根据操作需要），而不是作为每个操作附加的一整套资源。使用上述分配方案，可以实现微处理器资源的高效利用。

9. 发明授权

US5584038A Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed 失效
标题翻译：使用指示循环缓冲区的队列是否已遍历的换行符，循环缓冲区中的条目分配
公开(公告)号：US5584038A
公开(公告)日：1996-12-10
申请号：US633905
申请日：1996-04-17
申请人： David B. Papworth , Andrew F. Glew , Michael A. Fetterman , Glenn J. Hinton , Robert P. Colwell , Steven J. Griffith , Shantanu R. Gupta , Narayan Hegde
发明人： David B. Papworth , Andrew F. Glew , Michael A. Fetterman , Glenn J. Hinton , Robert P. Colwell , Steven J. Griffith , Shantanu R. Gupta , Narayan Hegde
IPC分类号： G06F5/10 , G06F5/14 , G06F9/38 , G06F12/00
CPC分类号： G06F5/14 , G06F9/3836 , G06F9/384 , G06F9/3844 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch anti speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries. The allocator utilizes an all or nothing allocation policy, such that either all or no incoming instructions are allocated during an allocation period.
摘要翻译：分配器为循环缓冲区分配条目。分配器接收在循环缓冲器的条目中存储数据的请求，并且生成头指针以标识不分配循环缓冲器条目的循环缓冲器中的起始条目。除了指向循环缓冲区中的条目之外，头指针还包括一个换行位。每次分配器遍历循环缓冲区的线性队列时，分配器将切换换行。生成尾指针，包括换行位，以标识分配循环缓冲区条目的循环缓冲区中的结尾条目。响应于条目请求，分配器顺序分配位于头部指针和尾部指针之间的请求的条目。分配器具有用于执行无序调度的推测执行的微处理器的应用程序。分配器被耦合到配置为循环缓冲器的重排序缓冲器，以允许分配条目。分配器利用全部或全部分配策略，使得在分配周期期间分配全部或者没有传入指令。

10. 发明授权

US5561814A Methods and apparatus for determining memory operating characteristics for given memory locations via assigned address ranges 失效
标题翻译：用于通过分配的地址范围确定给定存储器位置的存储器操作特性的方法和装置
公开(公告)号：US5561814A
公开(公告)日：1996-10-01
申请号：US171528
申请日：1993-12-22
申请人： Andrew F. Glew , Glenn J. Hinton , David B. Papworth , Michael A. Fetterman , Robert P. Colwell , Frederick J. Pollack
发明人： Andrew F. Glew , Glenn J. Hinton , David B. Papworth , Michael A. Fetterman , Robert P. Colwell , Frederick J. Pollack
IPC分类号： G06F12/08 , G06F12/10 , G06F13/10
CPC分类号： G06F12/0888 , G06F12/1027 , G06F2212/206
摘要： A circuit comprising a number of address range registers and complimentary decoding/matching circuits is provided to a processor for determining the memory type of a physical address, thereby allowing memory type to be determined as soon as the physical address is available in an execution stage preceding cache access. Additionally, a memory type field is provided to each address translation lookaside buffer entry of the data and instruction memory subsystem for storing the determined memory type. The memory type determination circuit is disposed in the page miss handler, thereby allowing memory type to be determined at the same time when the physical address is determined.
摘要翻译：包括多个地址范围寄存器和互补解码/匹配电路的电路被提供给处理器，用于确定物理地址的存储器类型，由此一旦物理地址在执行阶段中可用，就允许确定存储器类型缓存访问。此外，存储器类型字段被提供给用于存储确定的存储器类型的数据和指令存储器子系统的每个地址转换后备缓冲器入口。存储器类型确定电路设置在页面未命中处理器中，从而允许在确定物理地址的同时确定存储器类型。

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