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1. 发明授权

US5778245A Method and apparatus for dynamic allocation of multiple buffers in a processor 失效
标题翻译：用于在处理器中动态分配多个缓冲器的方法和装置
公开(公告)号：US5778245A
公开(公告)日：1998-07-07
申请号：US204861
申请日：1994-03-01
申请人： David B. Papworth , Andrew F. Glew , Glenn J. Hinton , Robert P. Colwell , Michael A. Fetterman , Shantanu R. Gupta , James S. Griffith
发明人： David B. Papworth , Andrew F. Glew , Glenn J. Hinton , Robert P. Colwell , Michael A. Fetterman , Shantanu R. Gupta , James S. Griffith
IPC分类号： G06F9/38 , G06F9/50 , G06F15/82
CPC分类号： G06F9/5016 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A method and apparatus for dynamically allocating entries of microprocessor resources to particular instructions in an efficient manner to efficiently utilize buffer size and resources. The pipelined and superscalar microprocessor is capable of speculatively executing instructions and also out-of-order processing. Resources within the microprocessor include a store buffer, a load buffer, a reorder buffer and a reservation station. The reorder buffer contains a larger set of physical registers and also contains information related to speculative instructions and the reservation station comprises information related to instructions pending execution. The load buffer is only allocated to load instructions and is valid for an instruction from allocation pipestage to instruction retirement. The store buffer is only allocated to store instructions and is valid for an instruction from allocation to store performance. The reservation station is allocated to most instructions and is valid for an instruction from allocation to instruction dispatch. The reorder buffer is allocated to all instructions and is valid for a given instruction from allocation to retirement. The load buffer, store buffer, and reorder buffer are sequentially allocated while the reservation station is not. Resource allocation is performed dynamically (as needed by the operation) rather than as a full set of resources attached to each operation. Using the above allocation scheme, efficient usage of the microprocessor resources is accomplished.
摘要翻译：一种用于以有效方式动态地将微处理器资源的条目分配给特定指令以有效利用缓冲器大小和资源的方法和装置。流水线和超标量微处理器能够推测性地执行指令并进行无序处理。微处理器内的资源包括存储缓冲器，加载缓冲器，重新排序缓冲器和保留站。重排序缓冲器包含较大的一组物理寄存器，并且还包含与推测指令相关的信息，并且保留站包括与待执行的指令相关的信息。加载缓冲区仅分配给加载指令，对从分配管理到指令退出的指令有效。存储缓冲区仅被分配用于存储指令，并且对于分配的指令有效以存储性能。保留站被分配给大多数指令，并且对于从分配到指令分派的指令是有效的。重新排序缓冲区被分配给所有指令，并且对于从分配到退休的给定指令是有效的。在保留站不存在的情况下顺序地分配负载缓冲器，存储缓冲器和重排序缓冲器。动态执行资源分配（根据操作需要），而不是作为每个操作附加的一整套资源。使用上述分配方案，可以实现微处理器资源的高效利用。

2. 发明授权

US5584038A Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed 失效
标题翻译：使用指示循环缓冲区的队列是否已遍历的换行符，循环缓冲区中的条目分配
公开(公告)号：US5584038A
公开(公告)日：1996-12-10
申请号：US633905
申请日：1996-04-17
申请人： David B. Papworth , Andrew F. Glew , Michael A. Fetterman , Glenn J. Hinton , Robert P. Colwell , Steven J. Griffith , Shantanu R. Gupta , Narayan Hegde
发明人： David B. Papworth , Andrew F. Glew , Michael A. Fetterman , Glenn J. Hinton , Robert P. Colwell , Steven J. Griffith , Shantanu R. Gupta , Narayan Hegde
IPC分类号： G06F5/10 , G06F5/14 , G06F9/38 , G06F12/00
CPC分类号： G06F5/14 , G06F9/3836 , G06F9/384 , G06F9/3844 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch anti speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries. The allocator utilizes an all or nothing allocation policy, such that either all or no incoming instructions are allocated during an allocation period.
摘要翻译：分配器为循环缓冲区分配条目。分配器接收在循环缓冲器的条目中存储数据的请求，并且生成头指针以标识不分配循环缓冲器条目的循环缓冲器中的起始条目。除了指向循环缓冲区中的条目之外，头指针还包括一个换行位。每次分配器遍历循环缓冲区的线性队列时，分配器将切换换行。生成尾指针，包括换行位，以标识分配循环缓冲区条目的循环缓冲区中的结尾条目。响应于条目请求，分配器顺序分配位于头部指针和尾部指针之间的请求的条目。分配器具有用于执行无序调度的推测执行的微处理器的应用程序。分配器被耦合到配置为循环缓冲器的重排序缓冲器，以允许分配条目。分配器利用全部或全部分配策略，使得在分配周期期间分配全部或者没有传入指令。

3. 发明授权

US5584037A Entry allocation in a circular buffer 失效
标题翻译：循环缓冲区中的条目分配
公开(公告)号：US5584037A
公开(公告)日：1996-12-10
申请号：US571377
申请日：1995-12-13
申请人： David B. Papworth , Andrew F. Glew , Michael A. Fetterman , Glenn J. Hinton , Robert P. Colwell , Steven J. Griffith , Shantanu R. Gupta , Narayan Hegde
发明人： David B. Papworth , Andrew F. Glew , Michael A. Fetterman , Glenn J. Hinton , Robert P. Colwell , Steven J. Griffith , Shantanu R. Gupta , Narayan Hegde
IPC分类号： G06F5/10 , G06F5/14 , G06F9/38 , G06F12/00
CPC分类号： G06F5/14 , G06F9/3836 , G06F9/384 , G06F9/3844 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch and speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries. The allocator utilizes an all or nothing allocation policy, such that either all or no incoming instructions are allocated during an allocation period.
摘要翻译：分配器为循环缓冲区分配条目。分配器接收在循环缓冲器的条目中存储数据的请求，并且生成头指针以标识不分配循环缓冲器条目的循环缓冲器中的起始条目。除了指向循环缓冲区中的条目之外，头指针还包括一个换行位。每次分配器遍历循环缓冲区的线性队列时，分配器将切换换行。生成尾指针，包括换行位，以标识分配循环缓冲区条目的循环缓冲区中的结尾条目。响应于条目请求，分配器顺序分配位于头部指针和尾部指针之间的请求的条目。分配器具有用于执行无序调度和推测执行的微处理器的应用。分配器被耦合到配置为循环缓冲器的重排序缓冲器，以允许分配条目。分配器利用全部或全部分配策略，使得在分配周期期间分配全部或者没有传入指令。

4. 发明授权

US5689674A Method and apparatus for binding instructions to dispatch ports of a reservation station 失效
标题翻译：用于绑定指令以分配保留站的端口的方法和装置
公开(公告)号：US5689674A
公开(公告)日：1997-11-18
申请号：US550745
申请日：1995-10-31
申请人： James S. Griffith , Shantanu R. Gupta , Glenn J. Hinton
发明人： James S. Griffith , Shantanu R. Gupta , Glenn J. Hinton
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A method and apparatus for binding instructions to dispatch ports in a reservation station includes a counter mechanism and a port identifier. The counter mechanism maintains a count of instructions which are pending dispatch from at least one of the dispatch ports. The port identifier receives an instruction and identifies to which of the dispatch ports the instruction is to be bound, based on the count of instructions maintained by the counter mechanism.
摘要翻译：用于绑定指令以在保留站中分派端口的方法和装置包括计数器机制和端口标识符。计数器机构保持正在从至少一个调度端口发送的指令的计数。端口标识符基于由计数器机制保持的指令的计数，接收指令并且识别指令将被绑定到哪个调度端口。

5. 发明授权

US5490280A Apparatus and method for entry allocation for a resource buffer 失效
标题翻译：资源缓冲区的入口分配装置和方法
公开(公告)号：US5490280A
公开(公告)日：1996-02-06
申请号：US267776
申请日：1994-06-28
申请人： Shantanu R. Gupta , James S. Griffith , Glenn J. Hinton
发明人： Shantanu R. Gupta , James S. Griffith , Glenn J. Hinton
IPC分类号： G06F9/38 , G06F3/00
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A method and apparatus for allocating a number of vacant entries of a buffer resource and generating a set of enable vectors based thereon for a set of issued instructions. A deallocation vector of a reservation station is searched in order to locate, within one clock cycle, the vacancies within the reservation station for storage of instruction information associated with several issued operations. Vacancies are indicated by bits of the deallocation vector. A general static and dynamic approach are disclosed for performing the vacant entry identification at high speed within a single clock cycle. Alternate embodiments are disclosed, based on the general approach, that divide the deallocation vector into separate portions (consecutive bits or interleaved) and process each portion based on the general approaches. Rotating priority reference points within the deallocation vector may be used to vary the starting point for vacancy location. Further, the vacancy search can be limited to finding only consecutive vacancies. A superscalar microprocessor using the above may, within one clock cycle, schedule a group of instructions from the instruction decoder to the reservation station for subsequent execution.
摘要翻译：一种分配缓冲器资源的空闲条目的方法和装置，并且基于一组发出的指令产生一组使能向量。搜索保留站的解除分配向量，以便在一个时钟周期内定位保留站内的空位，以存储与几个发布操作相关联的指令信息。空位由释放向量的位指示。公开了一种一般的静态和动态方法，用于在单个时钟周期内高速执行空闲条目识别。基于一般方法公开了替代实施例，其将解除分配向量划分为单独的部分（连续比特或交织），并且基于一般方法处理每个部分。可以使用释放向量内的旋转优先参考点来改变空位的起点。此外，空缺搜查可以限于仅找到连续的空缺。使用上述的超标量微处理器可以在一个时钟周期内调度从指令译码器到保留站的一组指令，用于随后的执行。

6. 发明授权

US5627984A Apparatus and method for entry allocation for a buffer resource utilizing an internal two cycle pipeline 失效
标题翻译：使用内部两循环流水线的缓冲资源进入分配的装置和方法
公开(公告)号：US5627984A
公开(公告)日：1997-05-06
申请号：US624187
申请日：1996-03-28
申请人： Shantanu R. Gupta , James S. Griffith
发明人： Shantanu R. Gupta , James S. Griffith
IPC分类号： G06F9/38 , G06F12/02
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A two cycle pipelined method and apparatus for allocating a number of vacant entries of a buffer resource and generating a set of enable vectors based thereon for a set of issued instructions. The procedure for determining the vacant entries is spread across two pipestages (clock cycles) of a pipelined superscalar processor. For each pipestage, the system receives information from the previous pipestage as to which entries were eligible for allocation but have not yet received instruction information as well as a set of speculative stall signals. For each pipestage, the reservation station informs the system as to which entries are vacant according to the reservation station's knowledge at that time; this is a preliminary deallocation vector. For each pipestage, the system also receives a list of the instructions for allocation to the reservation station for that cycle. The system formulates a modified deallocation vector from the above information by masking bits of the preliminary deallocation vector and also performs stall checking in the event there are not enough vacant entries. The system interrogates the modified deallocation vector to locate the vacancies within the reservation station for storage of instruction information associated with several issued operations. A general static and dynamic approach are disclosed for performing the vacant entry identification at high speed within a single clock cycle.
摘要翻译：一种用于分配缓冲器资源的多个空闲条目并且基于一组发出的指令生成一组使能向量的两循环流水线方法和装置。用于确定空闲条目的过程分布在流水线超标量处理器的两个管道（时钟周期）中。对于每个管道，系统从先前的管道接收关于哪些条目有资格分配但尚未收到指令信息以及一组推测失速信号的信息。对于每个管道，保留站根据当时的保留站的知识通知系统空闲的条目; 这是一个初步释放向量。对于每个管道，系统还接收用于该循环的分配给保留站的指令的列表。该系统通过屏蔽初步解除分配向量的比特来从上述信息中制定修改的解除分配向量，并且在没有足够的空闲条目的情况下也执行失速检查。系统询问修改的解除位置向量以定位保留站内的空位，用于存储与几个发布的操作相关联的指令信息。公开了一种一般的静态和动态方法，用于在单个时钟周期内高速执行空闲条目识别。

7. 发明授权

US5560025A Entry allocation apparatus and method of same 失效
标题翻译：条目分配装置及其方法
公开(公告)号：US5560025A
公开(公告)日：1996-09-24
申请号：US40659
申请日：1993-03-31
申请人： Shantanu R. Gupta , James S. Griffith
发明人： Shantanu R. Gupta , James S. Griffith
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3885 , G06F9/3836
摘要： A method and apparatus for searching for a pattern of values indicating vacancy within a reservation station. The present invention includes a method and apparatus for search a deallocation vector of an instruction scheduler in order to locate, within one clock cycle, a pattern of the first vacancies within the instruction scheduler for storage of instruction information associated with several microprocessor instructions. The present invention advantageously locates four vacant entries of the deallocation vector which specify the first four vacancies within a reservation station of the instruction scheduler and may be utilized to locate the first four vacant entries as well. The present invention performs the above processing utilizing high speed parallel processing methods so that the entire searching, reporting and updating functions, with regard to the deallocation vector, can be completed within one clock cycle. Two embodiments of the present invention, a static and a dynamic embodiment, are presented. Advantageously utilizing the present invention, a multi-instruction processing microprocessor may quickly and efficiently, within one clock cycle, schedule up to four instructions from the instruction decoder to the execution units of the microprocessor.
摘要翻译：一种用于搜索指示保留站内的空白的值的模式的方法和装置。本发明包括一种用于搜索指令调度器的释放向量的方法和装置，以便在一个时钟周期内定位指令调度器内的第一空位的模式，以存储与几个微处理器指令相关联的指令信息。本发明有利地定位了指定调度程序的保留站内的前四个空位的解除分配向量的四个空闲条目，并且还可以用于定位前四个空闲条目。本发明使用高速并行处理方法来执行上述处理，从而可以在一个时钟周期内完成关于取消分配向量的整个搜索，报告和更新功能。呈现本发明的两个实施例，静态和动态实施例。有利地利用本发明，多指令处理微处理器可以在一个时钟周期内快速且有效地安排从指令解码器到微处理器的执行单元的多达四条指令。

8. 发明授权

US5453708A Clocking scheme for latching of a domino output 失效
标题翻译：锁定多米诺骨牌输出的时钟方案
公开(公告)号：US5453708A
公开(公告)日：1995-09-26
申请号：US368335
申请日：1995-01-04
申请人： Shantanu R. Gupta , Thomas D. Fletcher
发明人： Shantanu R. Gupta , Thomas D. Fletcher
IPC分类号： H03K19/096 , H03K19/173
CPC分类号： H03K19/0963 , H03K19/1738
摘要： A clocking scheme provides for an improved latching of an output from a domino circuit by delaying a precharging of a domino node. The precharging delay is achieved by introducing the delay in the clocking circuitry which activates the precharging of the domino node. No delay is introduced in the data path in order not to delay the evaluation and transmission of the data signal. During one phase of a clocking cycle, the domino node is precharged to a predetermined logic state. Also during this precharge phase, an input latch couples an input data signal to the domino circuit. During the other phase of the clocking cycle, the domino circuit performs a logic operation based on the input signal. Also during this evaluation phase, an output latch latches the logic state of the domino output for transmission from the output latch. Subsequently, when the precharging phase commences, the precharging of the domino node is delayed until the output latch is completely deactivated, thereby ensuring that the precharge is not latched out to corrupt the data being transmitted.
摘要翻译：时钟方案通过延迟多米诺骨牌节点的预充电来提供对来自多米诺骨牌电路的输出的改进的锁存。通过在启动多米诺骨牌节点的预充电的时钟电路中引入延迟来实现预充电延迟。为了不延迟数据信号的评估和传输，在数据通路中不引入延迟。在时钟周期的一个阶段期间，多米诺骨骼节点被预充电到预定的逻辑状态。此外，在该预充电阶段期间，输入锁存器将输入数据信号耦合到多米诺骨牌电路。在时钟周期的另一阶段，多米诺骨电路基于输入信号执行逻辑运算。此外，在该评估阶段期间，输出锁存器锁存用于从输出锁存器传输的多米诺骨牌输出的逻辑状态。随后，当预充电阶段开始时，多米诺骨骼节点的预充电被延迟，直到输出锁存器被完全取消，从而确保预充电不被锁存以破坏被发送的数据。

9. 发明授权

US5524263A Method and apparatus for partial and full stall handling in allocation 失效
标题翻译：分配中部分和全部摊档处理的方法和装置
公开(公告)号：US5524263A
公开(公告)日：1996-06-04
申请号：US201560
申请日：1994-02-25
申请人： James S. Griffth , Shantanu R. Gupta , Narayan Hegde
发明人： James S. Griffth , Shantanu R. Gupta , Narayan Hegde
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/384 , G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3861
摘要： A method and apparatus for handling resource allocation during processor stall conditions. The instruction issue components of a processor are stalled (e.g., the issuance of new instruction is frozen) as a result of various stall conditions. One stall condition (full stall) occurs when an allocated buffer resource becomes full. Another stall condition (partial stall) occurs during register renaming and a given instruction sources a larger register width than the register alias table currently contains within the RAT buffer. This is a partial width data dependency and a partial stall is asserted. The present invention, upon detection of a full stall, does not allocate any buffer entries within the clock cycle that causing the full stall and resource pointers are not advanced and instructions issued during that clock cycle are not allocated. Within the clock cycle of the deassertion of the full stall, the resource buffers are allocated and the resource allocation pointers are updated. The present invention, upon detection of a partial stall, allocates a partial number of instructions within the clock cycle that causes the partial stall and updates a retirement entry pointer to the ROB but does not advance the resource pointers. Upon the clock cycle of the deassertion of the partial stall, the remainder of the instructions are allocated to the resource buffers and the resource pointers are advanced. In the event a full and partial stall are asserted concurrently, the full stall takes priority.
摘要翻译：一种用于在处理器停顿状态期间处理资源分配的方法和装置。作为各种失速条件的结果，处理器的指令发出组件被停止（例如，新指令的发出被冻结）。当分配的缓冲区资源变满时，会发生一个停顿状态（全停止）。在寄存器重命名期间发生另一个停顿条件（部分停止），并且给定的指令源于比RAT缓冲器中当前包含的寄存器别名表更大的寄存器宽度。这是部分宽度数据依赖关系，部分停止被断言。本发明在检测到完全失速后不在时钟周期内分配任何缓冲器条目，导致完全失速并且资源指针不被提前，并且在该时钟周期期间发出的指令未被分配。在完全失速消除的时钟周期内，分配资源缓冲区并更新资源分配指针。本发明在检测到部分失速后，在时钟周期内分配导致部分停止并将退出条目指针更新到ROB但不推进资源指针的部分指令数。在部分失速消除的时钟周期之后，剩余的指令被分配给资源缓冲区，资源指针被提前。在全部和部分失速同时被断言的情况下，完全失速优先。

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