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1. 发明授权

US6154825A Method and apparatus for addressing a memory resource comprising memory devices having multiple configurations 失效
标题翻译：用于寻址包括具有多种配置的存储器设备的存储器资源的方法和装置
公开(公告)号：US6154825A
公开(公告)日：2000-11-28
申请号：US814733
申请日：1997-03-07
申请人： Robert N. Murdoch , Michael W. Williams , Kuljit Bains , Narendra Khandekar
发明人： Robert N. Murdoch , Michael W. Williams , Kuljit Bains , Narendra Khandekar
IPC分类号： G06F12/02 , G06F12/06 , G06F12/10
CPC分类号： G06F12/06 , G06F12/0215
摘要： A method and apparatus for accessing a memory resource, such as an array of DRAM modules, is described. The methodology commences with the receipt of a memory address during a memory access cycle. A row address is then generated by selecting predetermined bits of the memory address as the row address. Concurrently with the generation of the row address, a determination is made as to the configuration of a memory device within the memory resource and targeted by the memory address. Thereafter, a column address is generated by selecting bits of the memory address as the column address based on the configuration of the targeted memory device. The time required for the determination of the configuration of the targeted memory device is thus absorbed within the time expended generating the row address.
摘要翻译：描述了用于访问诸如DRAM模块阵列之类的存储器资源的方法和装置。该方法开始于在存储器访问周期期间接收到存储器地址。然后通过选择存储器地址的预定位作为行地址来生成行地址。与行地址的产生同时，确定存储器资源内的存储器设备的配置并且由存储器地址对准。此后，基于目标存储器件的配置，通过选择存储器地址的位作为列地址来生成列地址。因此，确定目标存储器件的配置所需的时间在生成行地址的时间内被吸收。

2. 发明授权

US06199151B1 Apparatus and method for storing a device row indicator for use in a subsequent page-miss memory cycle 失效
标题翻译：用于存储用于随后的页错误存储器周期中的设备行指示器的装置和方法
公开(公告)号：US06199151B1
公开(公告)日：2001-03-06
申请号：US09092591
申请日：1998-06-05
申请人： Michael W. Williams , Mikal Hunsaker , Robert N. Murdoch
发明人： Michael W. Williams , Mikal Hunsaker , Robert N. Murdoch
IPC分类号： G06F1200
CPC分类号： G06F12/1027 , G06F12/0215 , G06F12/06
摘要： An apparatus and method for selecting a row of memory devices. A row value that indicates one of a plurality of chip select signals is stored in a storage element that is associated with a first address. A memory access request is received that includes the first address. The one of the plurality of chip select signals indicated by the row value is asserted to select one of a plurality of rows of memory devices.
摘要翻译：一种用于选择一行存储器件的装置和方法。指示多个芯片选择信号之一的行值被存储在与第一地址相关联的存储元件中。接收到包含第一个地址的存储器访问请求。由行值表示的多个片选信号之一被断言以选择多行存储器件中的一个。

3. 发明授权

US5860128A Method and apparatus for sampling data from a memory 失效
标题翻译：用于从存储器采样数据的方法和装置
公开(公告)号：US5860128A
公开(公告)日：1999-01-12
申请号：US724370
申请日：1996-10-01
申请人： Robert N. Murdoch , Michael W. Williams , Sathyamurthi Sadhasivan
发明人： Robert N. Murdoch , Michael W. Williams , Sathyamurthi Sadhasivan
IPC分类号： G11C7/10 , G11C8/18 , G11C29/50 , G06F12/06
CPC分类号： G11C7/106 , G11C29/50 , G11C7/1024 , G11C7/1051 , G11C7/1078 , G11C8/18 , G11C11/401
摘要： A novel method for performing memory accesses. Falling edges of a column address strobe (CAS) signal are used to cause dynamic random access memories (DRAMs) to drive data corresponding to the current address onto a data bus coupled to the input of a set of latches. A memory latch data (MLAD) signal is used to enable the set of latches. When the MLAD signal is asserted, the latches latch the data at the input in response to a falling edge of the CAS signal. When the MLAD signal is deasserted, the latch does not latch the data at the input in response to the falling edge of the CAS signal. Since the same signal (CAS) is used to control when the data is driven by the DRAMs and when the data is latched by the latches, the differences in output timings, signal path delays, and loads are avoided. The use of expensive timing compensation circuits and special tuning of these circuits for each circuit board redesign is thereby avoided.
摘要翻译：一种用于执行存储器访问的新方法。列地址选通（CAS）信号的下降沿用于使动态随机存取存储器（DRAM）将与当前地址相对应的数据驱动到耦合到一组锁存器的输入的数据总线上。存储器锁存数据（MLAD）信号用于使能该组锁存器。当MLAD信号被置位时，锁存器响应于CAS信号的下降沿在输入端锁存数据。当MLAD信号无效时，锁存器不会响应CAS信号的下降沿在输入端锁存数据。由于使用相同的信号（CAS）来控制数据由DRAM驱动，并且当数据被锁存器锁存时，避免了输出定时，信号路径延迟和负载的差异。因此避免了使用昂贵的定时补偿电路和对每个电路板进行重新设计的这些电路的特殊调谐。

4. 发明授权

US06370624B1 Configurable page closing method and apparatus for multi-port host bridges 失效
标题翻译：用于多端口主机桥的可配置的页面关闭方法和装置
公开(公告)号：US06370624B1
公开(公告)日：2002-04-09
申请号：US09712010
申请日：2000-11-13
申请人： Jasmin Ajanovic , Michael W. Williams , Robert N. Murdoch
发明人： Jasmin Ajanovic , Michael W. Williams , Robert N. Murdoch
IPC分类号： G06F1200
CPC分类号： G06F12/0215
摘要： A page closing method and apparatus for multi-port host bridges. According to a method disclosed, a plurality of memory access commands are received from a plurality of command ports. A command is selected from one of the command ports to be the next memory access command executed. A number of pages of memory are closed in response to the command selected as the next memory access command. The number of pages closed is determined at least in part on which command port provides the next memory access command.
摘要翻译：一种用于多端口主机桥的页面关闭方法和装置。根据所公开的方法，从多个命令端口接收多个存储器访问命令。从命令端口之一中选择一个命令作为执行的下一个存储器访问命令。响应于作为下一个存储器访问命令选择的命令，多个页面的存储器被关闭。关闭的页数至少部分地由哪个命令端口提供下一个存储器访问命令确定。

5. 发明授权

US06199145B1 Configurable page closing method and apparatus for multi-port host bridges 失效
标题翻译：用于多端口主机桥的可配置的页面关闭方法和装置
公开(公告)号：US06199145B1
公开(公告)日：2001-03-06
申请号：US09032434
申请日：1998-02-27
申请人： Jasmin Ajanovic , Michael W. Williams , Robert N. Murdoch
发明人： Jasmin Ajanovic , Michael W. Williams , Robert N. Murdoch
IPC分类号： G06F1200
CPC分类号： G06F12/0215
摘要： A page closing method and apparatus for multi-port host bridges. According to a method disclosed, a plurality of memory access commands are received from a plurality of command ports. A command is selected from one of the command ports to be the next memory access command executed. A number of pages of memory are closed in response to the command selected as the next memory access command. The number of pages closed is determined at least in part on which command port provides the next memory access command.
摘要翻译：一种用于多端口主机桥的页面关闭方法和装置。根据所公开的方法，从多个命令端口接收多个存储器访问命令。从命令端口之一中选择一个命令作为执行的下一个存储器访问命令。响应于作为下一个存储器访问命令选择的命令，多个页面的存储器被关闭。关闭的页数至少部分地由哪个命令端口提供下一个存储器访问命令确定。

6. 发明授权

US06226730B1 Achieving page hit memory cycles on a virtual address reference 失效
标题翻译：实现虚拟地址引用上的页面命中内存循环
公开(公告)号：US06226730B1
公开(公告)日：2001-05-01
申请号：US09092426
申请日：1998-06-05
申请人： Robert N. Murdoch , Michael W. Williams
发明人： Robert N. Murdoch , Michael W. Williams
IPC分类号： G06F1210
CPC分类号： G06F12/0215
摘要： An apparatus and method for accessing a memory. A source address that includes a page address and a page offset is received. The page address requires translation in order to form a first address that can be used to transfer data from a row of memory cells into a sense amplifier array in a memory. The page address is compared to contents of one or more page registers to determine if the data is present in the sense amplifier array as a result of a previous memory access. A second address is asserted to access a portion of the data if the data is determined to be present in the sense amplifier array.
摘要翻译：一种用于访问存储器的装置和方法。接收包含页面地址和页面偏移的源地址。页面地址需要转换以形成可以用于将数据从一行存储器单元传送到存储器中的读出放大器阵列的第一地址。将页面地址与一个或多个页面寄存器的内容进行比较，以确定数据是否作为先前存储器访问的结果存在于读出放大器阵列中。如果数据被确定为存在于读出放大器阵列中，则第二地址被断言以访问数据的一部分。

7. 发明授权

US4901235A Data processing system having unique multilevel microcode architecture 失效
标题翻译：数据处理系统具有独特的多级微代码架构
公开(公告)号：US4901235A
公开(公告)日：1990-02-13
申请号：US546572
申请日：1983-10-28
申请人： Chandra R. Vora , Donald C. Wiser , Mark B. Hecker , Robert N. Murdoch
发明人： Chandra R. Vora , Donald C. Wiser , Mark B. Hecker , Robert N. Murdoch
IPC分类号： G06F9/22 , G06F9/28 , G06F9/38
CPC分类号： G06F9/223 , G06F9/28 , G06F9/3885
摘要： A data processing system which includes a central processor unit which has an arithmetic logic unit (ALU) for performing fixed point arithmetic operations and a separate floating point unit (FPU) for performing floating point operations and which uses multi-level microcode architecture wherein each unit has its own control store (a "horizontal" store) which responds to addresses of execution control signals supplied thereto from a common control store (a "vertical" store) to produce horizontal microinstructions for performing ALU and FPU operations, respectively. Selected ones of such addresses are recognized for ALU operations by the CPU control store only, other selected ones are recognized for FPU operations by the FPU control store only, while still other selected ones are recognized for both ALU and FPU operations by both control stores so that such operations can be performed simultaneously in parallel.
摘要翻译：一种数据处理系统，其包括具有用于执行定点算术运算的算术逻辑单元（ALU）和用于执行浮点运算的单独浮点单元（FPU）的中央处理器单元，并且使用多级微代码架构，其中每个单元具有其自己的控制存储器（“水平”存储器），其响应于从公共控制存储器（“垂直”存储器）提供的执行控制信号的地址，以分别产生用于执行ALU和FPU操作的水平微指令。所选择的这些地址仅由CPU控制存储器识别用于ALU操作，仅由FPU控制存储器识别用于FPU操作的其他选择的操作，同时由两个控制存储器为ALU和FPU操作识别其他选定的一个。这样的操作可以并行同时执行。

8. 发明授权

US5894567A Mechanism for enabling multi-bit counter values to reliably cross between clocking domains 失效
标题翻译：使多位计数器值可靠地跨越时钟域之间的机制
公开(公告)号：US5894567A
公开(公告)日：1999-04-13
申请号：US536109
申请日：1995-09-29
申请人： James M. Dodd , Robert N. Murdoch
发明人： James M. Dodd , Robert N. Murdoch
IPC分类号： G06F5/06 , G06F13/40 , G06F1/04
CPC分类号： G06F5/06 , G06F13/405
摘要： A queue structure for transmitting a multiple-bit signal from a first sub-system operating in a first clocking domain in a computer system to a second sub-system operating in a second clocking domain in the computer system is disclosed. The queue structure comprises a queue data latch having a plurality of storage elements, wherein each of the plurality of storage elements can store the multiple-bit signal from the first sub-system. A load pointer is used for generating a first multiple-bit count indicating one of the plurality of storage element for storing the multiple-bit signal. A synchronization unit is coupled to the load pointer for receiving the first multiple-bit count. The synchronization unit outputs the multiple-bit count at the second sub-system when the multiple-bit signal is ready to be sampled in the second clocking domain.
摘要翻译：公开了一种用于从在计算机系统中的第一计时域中操作的第一子系统将多比特信号发送到在计算机系统中的第二计时域中操作的第二子系统的队列结构。队列结构包括具有多个存储元件的队列数据锁存器，其中多个存储元件中的每一个可以存储来自第一子系统的多位信号。负载指针用于产生指示用于存储多位信号的多个存储元件之一的第一多位计数。同步单元耦合到负载指针，用于接收第一多位计数。当多位信号准备好在第二计时域采样时，同步单元输出第二子系统的多位计数。

9. 发明授权

US4046083A Merchandise display shelving assembly 失效
标题翻译：商品展示架组装
公开(公告)号：US4046083A
公开(公告)日：1977-09-06
申请号：US673694
申请日：1976-04-05
申请人： Robert N. Murdoch , Vincent M. Travaglio , Michael L. Magnifico
发明人： Robert N. Murdoch , Vincent M. Travaglio , Michael L. Magnifico
IPC分类号： A47F5/10 , A47B9/00
CPC分类号： A47F5/103
摘要： Spaced hollow vertical posts are supported by base means. Each post has a pair of spaced substantially coextensive vertically elongated flat panel bars of substantial thickness with vertical opposite side edges and a series of vertically spaced shelf bracket connection apertures intermediate the edges, there being a pair of substantially coextensive vertical opposite side channel members of relatively thin gauge material to which the side edges of the panel bars are secured in edgewise abutment. Stabilizing bar means have angular attachment terminal tongues or vertical finishing strips may be engaged with transverse attachments straps on the channels. Gusset members in the base structure support the posts and are formed from horizontally elongated vertically standing panels having plate attachment structure at their ends. The base includes detachable shelf and trim structure. At one end of the assembly, merchandise promotional display extension may be provided comprising a transverse vertical panel and shelf-supporting structure and a horizontal base deck.
摘要翻译：间距中空的垂直柱由底座支撑。每个柱具有一对具有相当厚度的基本上共同延伸的垂直细长平板条，其具有垂直相对的侧边缘和在边缘之间的一系列垂直间隔的搁架支架连接孔，存在一对相对较大的共同延伸的垂直相对侧通道构件薄板材料，面板条的侧边缘固定在边缘基台上。稳定杆装置具有角度附接端子舌片或垂直整理条可以与通道上的横向附件带接合。底座结构中的角撑构件支撑柱，并且由在其端部具有板附接结构的水平细长的垂直立面板形成。底座包括可拆卸的货架和装饰结构。在组装的一端，可以提供商品促销展示延伸部，包括横向垂直面板和搁架支撑结构以及水平底座。

10. 发明授权

US5889974A Method and apparatus for the detection of reordering hazards 失效
标题翻译：检测重排序危害的方法和装置
公开(公告)号：US5889974A
公开(公告)日：1999-03-30
申请号：US774516
申请日：1996-12-30
申请人： David J. Harriman , Robert N. Murdoch
发明人： David J. Harriman , Robert N. Murdoch
IPC分类号： G06F9/38 , G06F11/28 , G06F13/00
CPC分类号： G06F9/3834 , G06F11/28 , G06F9/3836 , G06F9/3855
摘要： In a computer system processing out of order commands, a method for detecting situations in which errors could be caused by execution of an out of order command. The method includes the steps of receiving a first address of a first type and receiving a next address of the first type. Information is accumulated regarding differences between the first address and the next address. The method also includes receiving an address of a second type and using the accumulated information to determine whether the address of the second type is an address associated with a command whose execution can create a hazard. A hazard indication is generated if it is determined that the address of the second type is an address associated with a command whose execution can create a hazard. In one embodiment, the first type of address is an address associated with a first type of command and the second type of address is an address associated with a second type of command. In another embodiment, the first type of command and the second type of command are the same type of command.
摘要翻译：在处理不合格命令的计算机系统中，检测可能由于执行无序命令而导致错误的情况的方法。该方法包括以下步骤：接收第一类型的第一地址并接收第一类型的下一地址。有关第一个地址和下一个地址之间的差异的信息。该方法还包括接收第二类型的地址并使用累积信息来确定第二类型的地址是否是与其执行可能产生危险的命令相关联的地址。如果确定第二类型的地址是与其执行可能产生危险的命令相关联的地址，则生成危险指示。在一个实施例中，第一类型的地址是与第一类型的命令相关联的地址，并且第二类型的地址是与第二类型的命令相关联的地址。在另一个实施例中，第一类型的命令和第二类型的命令是相同类型的命令。

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