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1. 发明授权

US07165125B2 Buffer sharing in host controller 失效
标题翻译：主机控制器中的缓冲区共享
公开(公告)号：US07165125B2
公开(公告)日：2007-01-16
申请号：US10817572
申请日：2004-04-02
申请人： Robert Lissel , Bernd Schönfelder , Frank Barth
发明人： Robert Lissel , Bernd Schönfelder , Frank Barth
IPC分类号： G06F31/20 , G06F13/00
CPC分类号： G06F3/0661 , G06F3/0607 , G06F3/0674 , G06F13/28 , G06F13/385
摘要： A storage device host controller such as an SATA (Serial ATA) host controller and a corresponding method are provided for performing host-to-device and device-to-host communications in a PIO (Programmed I/O) data transfer mode and a DMA (Direct Memory Access) data transfer mode. The host controller comprises a buffer unit for buffering data and a data stream selection unit for selecting a data stream for submission to the buffer unit. The data stream selection unit is connected to receive at any one time at least one of a host-to-device data stream in the PIO data transfer mode, a host-to-device data stream in the DMA data transfer mode, a device-to-host data stream in the PIO data transfer mode, and a device-to-host data stream in the DMA data transfer mode, and select from the received data streams the data stream to be submitted to the buffer unit.
摘要翻译：提供诸如SATA（串行ATA）主机控制器和相应方法的存储设备主机控制器，用于在PIO（编程I / O）数据传输模式和DMA中执行主机到设备和设备到主机的通信（直接存储器访问）数据传输模式。主机控制器包括用于缓冲数据的缓冲器单元和用于选择用于提交到缓冲器单元的数据流的数据流选择单元。数据流选择单元被连接以在任何一个时间接收PIO数据传送模式的主机到设备数据流中的至少一个，DMA数据传送模式中的主机到设备数据流，在PIO数据传送模式中的主机数据流，以及DMA数据传送模式中的设备到主机数据流，并从所接收的数据流中选择要提交给缓冲器单元的数据流。

2. 发明申请

US20050120150A1 Buffer sharing in host controller 失效
标题翻译：主机控制器中的缓冲区共享
公开(公告)号：US20050120150A1
公开(公告)日：2005-06-02
申请号：US10817572
申请日：2004-04-02
申请人： Robert Lissel , Bernd Schonfelder , Frank Barth
发明人： Robert Lissel , Bernd Schonfelder , Frank Barth
IPC分类号： G06F3/06 , G06F13/14 , G06F13/28 , G06F13/38
CPC分类号： G06F3/0661 , G06F3/0607 , G06F3/0674 , G06F13/28 , G06F13/385
摘要： A storage device host controller such as an SATA (Serial ATA) host controller and a corresponding method are provided for performing host-to-device and device-to-host communications in a PIO (Programmed I/O) data transfer mode and a DMA (Direct Memory Access) data transfer mode. The host controller comprises a buffer unit for buffering data and a data stream selection unit for selecting a data stream for submission to the buffer unit. The data stream selection unit is connected to receive at any one time at least one of a host-to-device data stream in the PIO data transfer mode, a host-to-device data stream in the DMA data transfer mode, a device-to-host data stream in the PIO data transfer mode, and a device-to-host data stream in the DMA data transfer mode, and select from the received data streams the data stream to be submitted to the buffer unit.
摘要翻译：提供诸如SATA（串行ATA）主机控制器和相应方法的存储设备主机控制器，用于在PIO（编程I / O）数据传输模式和DMA中执行主机到设备和设备到主机的通信（直接存储器访问）数据传输模式。主机控制器包括用于缓冲数据的缓冲器单元和用于选择用于提交到缓冲器单元的数据流的数据流选择单元。数据流选择单元被连接以在任何一个时间接收PIO数据传送模式的主机到设备数据流中的至少一个，DMA数据传送模式中的主机到设备数据流，在PIO数据传送模式中的主机数据流，以及DMA数据传送模式中的设备到主机数据流，并从所接收的数据流中选择要提交给缓冲器单元的数据流。

3. 发明申请

US20130298863A1 IGNITION SYSTEM AND OPERATING METHOD FOR SAME 审中-公开
标题翻译：点火系统及其操作方法
公开(公告)号：US20130298863A1
公开(公告)日：2013-11-14
申请号：US13885576
申请日：2011-09-13
申请人： Karl-Heinz Nuebel , Manfred Vogel , Frank Barth , Martin Weinrotter
发明人： Karl-Heinz Nuebel , Manfred Vogel , Frank Barth , Martin Weinrotter
IPC分类号： F02P23/04
CPC分类号： F02P23/04 , F02D41/22 , F02P17/12 , Y02T10/40
摘要： An ignition system is described, in particular for an internal combustion engine of a motor vehicle, having a laser spark plug, a pump module for supplying the laser spark plug with pump radiation, and an optical fiber device for transmitting the pump radiation from the pump module to the laser spark plug. At least two separate signal transmission devices which each extend at least partially along the optical fiber device, and an evaluation unit, which is designed to act on each of the signal transmission devices with a test signal, to evaluate a response signal of the signal transmission devices which results from the particular test signal, and from the response signal to deduce an operating state of the corresponding signal transmission device, are provided.
摘要翻译：具体涉及一种具有激光火花塞的激光火花塞，用于向激光火花塞提供泵浦辐射的泵模块以及用于从泵送出泵浦辐射的光纤装置的点火系统，特别是用于机动车辆的内燃机模块到激光火花塞。至少两个单独的信号传输设备，其每个至少部分地沿着光纤设备延伸，以及评估单元，其被设计为用测试信号作用在每个信号传输设备上，以评估信号传输的响应信号提供由特定测试信号产生的设备和从响应信号推断对应的信号传输设备的操作状态。

4. 发明授权

US07225290B2 ATA and SATA compliant controller 有权
标题翻译： ATA和SATA兼容控制器
公开(公告)号：US07225290B2
公开(公告)日：2007-05-29
申请号：US10184434
申请日：2002-06-27
申请人： Frank Barth , Henry Drescher , Alexander Krebs
发明人： Frank Barth , Henry Drescher , Alexander Krebs
IPC分类号： G06F13/00
CPC分类号： G06F13/385 , G06F3/0607 , G06F3/0635 , G06F3/0661 , G06F3/0689
摘要： An ATA (Advanced Technology Attachment) controller is provided that comprises at least one parallel port for connecting to at least one ATA compliant storage device, and at least one serial port for connecting to at least one SATA (Serial ATA) compliant storage device. Further, there is a port switching unit provided for switching to at least one of the parallel and serial ports to enable data transfer to and/or from a storage device connected to the port. This enables a software driven reconfiguration making it possible to switch between a mode where the controller behaves like a conventional ATA controller, and a mode where the controller behaves like a conventional SATA controller. A significant amount of hardware may be reused.
摘要翻译：提供了一种ATA（高级技术附件）控制器，其包括用于连接至少一个符合ATA的存储设备的至少一个并行端口以及用于连接至少一个SATA（串行ATA）兼容存储设备的至少一个串行端口。此外，存在端口切换单元，用于切换到至少一个并行端口和串行端口，以使数据传输到和/或连接到端口的存储设备。这使得能够进行软件驱动的重新配置，使得可以在控制器的行为像传统的ATA控制器的模式和控制器的行为像传统的SATA控制器的模式之间切换。大量的硬件可能会重复使用。

5. 发明授权

US07181561B2 Ordering rule controlled command storage 有权
标题翻译：订购规则控制命令存储
公开(公告)号：US07181561B2
公开(公告)日：2007-02-20
申请号：US10465014
申请日：2003-06-19
申请人： Frank Barth , Thomas Kunjan
发明人： Frank Barth , Thomas Kunjan
IPC分类号： G06F13/14 , G06F13/42 , G06F5/00 , G06F13/36
CPC分类号： G06F13/4031
摘要： A command storage technique that fulfils ordering rules is provided. This technique may be used in HyperTransport compliant southbridge devices. A command transmit engine comprises a command storage unit that is adapted to receive incoming commands of different command types and store the command in the order in which the commands were received. The command transmit engine further comprises an ordering rule controller that is connected to the command storage unit to select stored commands to be transmitted. The ordering rule controller is adapted to perform the selection according to predefined command ordering rules. The command ordering rules are command type dependent.
摘要翻译：提供了满足排序规则的命令存储技术。此技术可用于HyperTransport兼容南桥设备。命令发送引擎包括命令存储单元，该命令存储单元适于接收不同命令类型的输入命令，并按照接收命令的顺序存储命令。命令发送引擎还包括排序规则控制器，其连接到命令存储单元以选择存储的要发送的命令。排序规则控制器适于根据预定义的命令排序规则执行选择。命令排序规则取决于命令类型。

6. 发明申请

US20130298864A1 COVERING DEVICE FOR A SPARK PLUG SHAFT AND OPTICAL FIBER DEVICE FOR A LASER SPARK PLUG 审中-公开
标题翻译：用于激光火花塞的火花塞轴和光纤装置的覆盖装置
公开(公告)号：US20130298864A1
公开(公告)日：2013-11-14
申请号：US13885297
申请日：2011-09-13
申请人： Karl-Heinz Nuebel , Manfred Vogel , Frank Barth , Martin Weinrotter
发明人： Karl-Heinz Nuebel , Manfred Vogel , Frank Barth , Martin Weinrotter
IPC分类号： H01T13/06
CPC分类号： H01T13/06 , F02F1/242 , F02P23/04
摘要： A covering device for a spark plug shaft of an internal combustion engine has a fastening element provided for mechanically fastening the covering device to a target system, the fastening element being configured to electrically conductively connect at least one electric conductor to the covering device (100) and/or the target system.
摘要翻译：一种用于内燃机的火花塞轴的覆盖装置，具有用于将覆盖装置机械地紧固到目标系统的紧固元件，所述紧固元件构造成将至少一个电导体导电地连接到覆盖装置（100）和/或目标系统。

7. 发明授权

US07519755B2 Combined command and response on-chip data interface for a computer system chipset 失效
标题翻译：用于计算机系统芯片组的命令和响应片上数据接口
公开(公告)号：US07519755B2
公开(公告)日：2009-04-14
申请号：US10964884
申请日：2004-10-14
申请人： Thomas Kunjan , Joerg Winkler , Frank Barth
发明人： Thomas Kunjan , Joerg Winkler , Frank Barth
IPC分类号： G06F13/00
CPC分类号： G06F13/4273
摘要： An integrated circuit chip, particularly a southbridge, is provided that has a first and a second circuit unit. Each circuit unit can send requests to the other one and send back a response when receiving a request that requires a response. The first circuit unit is connected to the second circuit unit to send to the second circuit unit request data relating to a request to be sent by the first circuit unit and response data relating to a response to be sent by the first circuit unit over a shared signal line.
摘要翻译：提供具有第一和第二电路单元的集成电路芯片，特别是南桥。每个电路单元可以向另一个电路单元发送请求，并在接收到需要响应的请求时发送响应。第一电路单元连接到第二电路单元，以向第二电路单元发送与由第一电路单元发送的请求相关的数据，以及与第一电路单元通过共享的要发送的响应有关的响应数据信号线。

8. 发明授权

US06839654B2 Debug interface for an event timer apparatus 失效
标题翻译：事件定时器设备的调试接口
公开(公告)号：US06839654B2
公开(公告)日：2005-01-04
申请号：US10361089
申请日：2003-02-07
申请人： René Röllig , Jens Meyer , Frank Barth , Alexander Krebs
发明人： René Röllig , Jens Meyer , Frank Barth , Alexander Krebs
IPC分类号： G06F1/14 , G06F11/36 , G04F10/00
CPC分类号： G06F11/3648 , G06F1/14 , G06F11/3656
摘要： An on-chip event timer apparatus including a hardware timer and a debug interface. The hardware timer includes at least an up-counter for counting clocks of a clock signal, a match register for storing a programmable count value, and a comparator for monitoring whether the up-counter's count value matches the count value of the match register. The debug interface includes enable control unit for enabling the up-counter's operation based on a pre-defined relationship between a state of an enabled signal supplied to said up-counter and an internal state of the hardware timer. Additionally, the debug interface may comprise a clock divider connected to the enable control unit to reduce the clock's frequency in accordance with a pre-programmed divider value. Based on the received clock with the reduced clock frequency, the enable control unit adapts the up-counter's processing speed to the reduced clock frequency.

9. 发明授权

US06718356B1 In-place operation method and apparatus for minimizing the memory of radix-r FFTs using maximum throughput butterflies 失效
标题翻译：使用最大吞吐量蝴蝶最小化radix-r FFT存储器的就地操作方法和装置
公开(公告)号：US06718356B1
公开(公告)日：2004-04-06
申请号：US09595409
申请日：2000-06-16
申请人： Stephan Rosner , Frank Barth
发明人： Stephan Rosner , Frank Barth
IPC分类号： G06F1500
CPC分类号： G06F17/142
摘要： The invention relates generally to radix-r FFTs (Fast Fourier Transforms), and more particularly to a method and an apparatus for assigning data samples to memory when computing a radix-r FFT. In one embodiment, the apparatus comprises a plurality of memory banks for storing the data samples, a memory bank counter indicating the memory banks, a data sample counter for counting an increment of the data samples, a region difference counter for counting a region difference change of a butterfly stage, a computer program having the current values of the data sample counter and the region difference counter as input values for determining whether the fractional part of the current data sample value divided by the current region difference value equals zero, and a multiplexer for multiplexing the current data sample to an assigned memory bank if the fractional part is not equal zero.
摘要翻译：本发明一般涉及基数FFT（快速傅里叶变换），更具体地说，涉及一种在计算基数r FFT时将数据样本分配给存储器的方法和装置。在一个实施例中，该装置包括用于存储数据样本的多个存储器组，指示存储体的存储器组计数器，用于对数据采样的增量进行计数的数据采样计数器，用于计数区域差变化的区域差计数器蝶形阶段的计算机程序，具有数据采样计数器的当前值和区域差计数器的计算机程序作为用于确定当前数据采样值的当前数据采样值的当前区间差值是否等于零的输入值;以及多路复用器如果分数部分不等于零，则将当前数据样本多路复用到分配的存储体。

10. 发明申请

US20060069974A1 One-hot encoded instruction register for boundary scan test compliant devices 审中-公开
标题翻译：用于边界扫描测试兼容设备的单热编码指令寄存器
公开(公告)号：US20060069974A1
公开(公告)日：2006-03-30
申请号：US11011398
申请日：2004-12-14
申请人： Thomas Herrmann , Frank Barth
发明人： Thomas Herrmann , Frank Barth
IPC分类号： G01R31/28
CPC分类号： G01R31/318555 , G01R31/318572
摘要： An integrated circuit chip operable in a plurality of Boundary Scan test modes in which at least a part of the circuitry comprised in the integrated circuit chip is tested is provided. The integrated circuit chip comprises a Boundary Scan register and an instruction register. The Boundary Scan register is arranged to perform a test on the tested part of the circuitry by applying a test signal to the tested part of the circuitry and/or storing an output of the tested part of the circuitry in accordance with one of the Boundary Scan test modes. The instruction register is arranged to store a one-hot encoded instruction identifying one of the Boundary Scan test modes. The Boundary Scan register is further arranged to extract which test to perform on the tested part of the circuitry from the one-hot encoded instruction stored in the instruction register. The integrated circuit chip and corresponding methods and hardware devices may benefit from increased test flexibility and reduced time to market.
摘要翻译：提供可在多个边界扫描测试模式中操作的集成电路芯片，其中测试集成电路芯片中包括的电路的至少一部分。集成电路芯片包括边界扫描寄存器和指令寄存器。边界扫描寄存器被布置成通过将测试信号施加到电路的测试部分和/或根据边界扫描中的一个存储电路的测试部分的输出来对所测试的部分电路进行测试测试模式。指令寄存器被设置为存储识别边界扫描测试模式之一的单热编码指令。边界扫描寄存器还被布置为从存储在指令寄存器中的单热编码指令中提取在电路的测试部分上执行哪个测试。集成电路芯片和相应的方法和硬件设备可以从增加的测试灵活性和缩短上市时间中受益。

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