专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5190228A Coffee grinder mount assembly 失效
标题翻译：咖啡研磨机座组件
公开(公告)号：US5190228A
公开(公告)日：1993-03-02
申请号：US769868
申请日：1991-10-01
申请人： Leonard A. Ficken , Robert J. Reese , Andrew F. Poag
发明人： Leonard A. Ficken , Robert J. Reese , Andrew F. Poag
IPC分类号： A47J42/48
CPC分类号： A47J42/48
摘要： A coffee grinder mount assembly for mounting a coffee grinder to a housing by a support member. The assembly located adjacent a coffee bean storage bin for receiving coffee beans therefrom for grinding. The assembly having a mounting bracket for supporting the coffee grinder and fixedly attaching it to the housing. The mounting bracket including a sliding mechanism for moving the coffee grinder between an operating position where the coffee grinder may be operated to grind coffee or like food product suitable for brewing, and a servicing position where the coffee grinder is disposed remote from the storage bin. The coffee grinder being movable with the sliding mechanism in a linear direction away from the operating position and then pivotable with the sliding mechanism to the servicing position.
摘要翻译：一种用于通过支撑构件将咖啡研磨器安装到壳体的咖啡研磨机安装组件。该组件位于咖啡豆储存箱附近，用于接收咖啡豆用于研磨。该组件具有用于支撑咖啡研磨器并将其固定地附接到壳体的安装支架。安装支架包括用于在咖啡研磨机可操作的咖啡研磨机可操作以研磨咖啡或适合于冲泡的食品的操作位置之间移动咖啡研磨机的滑动机构以及咖啡研磨机远离收纳箱设置的维修位置。咖啡研磨机可以通过滑动机构在远离操作位置的线性方向上移动，然后可与滑动机构一起转动到维修位置。

2. 发明授权

US5265518A Dual brewer for tea and coffee 失效
标题翻译：双啤酒茶和咖啡
公开(公告)号：US5265518A
公开(公告)日：1993-11-30
申请号：US971932
申请日：1992-11-05
申请人： Robert J. Reese , Andrew F. Poag
发明人： Robert J. Reese , Andrew F. Poag
IPC分类号： A47J31/00 , A47J31/32 , A47J31/40 , G07F13/06
CPC分类号： A47J31/32 , A47J31/40 , G07F13/065
摘要： A dual brewing system for a vending machine in which a pair of separate brewers are mounted for simultaneous movement through a brewing and dumping cycle even though only one of the brewers is actually used to brew a beverage, such as tea or coffee, at a time. A filter paper feed mechanism is provided for one of the brewers used primarily for coffee. The paper feed mechanism is controlled so that it is only advance after the brewer which it is associated with is used and not when the other brewer is used.

3. 发明授权

US09473333B2 Communications system via data scrambling and associated methods 有权
标题翻译：通信系统通过数据加扰及相关方法
公开(公告)号：US09473333B2
公开(公告)日：2016-10-18
申请号：US12028953
申请日：2008-02-11
申请人： Daniel M. Dreps , Frank D. Ferralolo , Robert J. Reese , Martin L. Schmatz
发明人： Daniel M. Dreps , Frank D. Ferralolo , Robert J. Reese , Martin L. Schmatz
IPC分类号： H04L9/00 , H04L25/03
CPC分类号： H04L25/03866
摘要： A communications system that may include a transmitter, a receiver, connected over a communications network. A communication link on the communications network may transfer data between the transmitter and the receiver. The system may also include a logic unit to scramble a plurality of portions of the data at the transmitter based upon the communication link and may unscramble the plurality of portions of the data at the receiver. As a result, the logic unit may provide improved performance of the communication link and/or reduced power consumption of the communication link.
摘要翻译：可以包括通过通信网络连接的发射机，接收机的通信系统。通信网络上的通信链路可以在发射机和接收机之间传送数据。系统还可以包括逻辑单元，用于基于通信链路在发射机处对数据的多个部分进行加扰，并且可以在接收器处解扰数据的多个部分。结果，逻辑单元可以提供通信链路的改进的性能和/或通信链路的降低的功耗。

4. 发明授权

US08265406B2 Parallel entropy encoding of dependent image blocks 有权
标题翻译：依赖图像块的并行熵编码
公开(公告)号：US08265406B2
公开(公告)日：2012-09-11
申请号：US12958516
申请日：2010-12-02
申请人： Robert J. Reese
发明人： Robert J. Reese
IPC分类号： G06K9/36
CPC分类号： H04N19/436 , H04N19/91
摘要： A method of entropy encoding image or video data may include entropy encoding a number of blocks independently and in parallel to generate a number of bit streams. At least one of the number of bit streams may include an assumed value in place of a value that would be determined by another bit stream. The method may also include selectively correcting the assumed value based on a value in another one of the number of bit streams. The number of bit streams may be combined into an output, entropy encoded bit stream corresponding to the number of blocks.
摘要翻译：对图像或视频数据进行熵编码的方法可以包括独立地并行并行地编码多个块来生成多个比特流。多个比特流中的至少一个可以包括假定值来代替由另一个比特流确定的值。该方法还可以包括基于多个比特流中的另一个中的值来选择性地校正假定值。比特流的数量可以被组合成与块数相对应的输出熵编码比特流。

5. 发明授权

US08259989B2 Identifying image content 有权
标题翻译：识别图像内容
公开(公告)号：US08259989B2
公开(公告)日：2012-09-04
申请号：US11263758
申请日：2005-10-31
申请人： Sudheer Sirivara , Jeffrey S. McVeigh , Robert J. Reese
发明人： Sudheer Sirivara , Jeffrey S. McVeigh , Robert J. Reese
IPC分类号： G06K9/00
CPC分类号： H04N21/4788 , G06F21/10 , H04N1/00002 , H04N1/00005 , H04N1/00037 , H04N1/00045 , H04N1/00925 , H04N7/165 , H04N21/23418 , H04N21/2541 , H04N21/8355 , H04N2201/3246 , H04N2201/3274 , Y10S707/99936
摘要： Identifying content and authorizing sharing thereof based at least in part on extracting feature data from content to be shared and comparing this extracted feature data against a database of extracted feature data for various reference content. When the content to be shared is matched to reference content in the database, sharing may be simply rejected, or rights associated with the reference content may be inspected to facilitate determining authorization.
摘要翻译：至少部分地基于从要共享的内容中提取特征数据来识别内容并授权其共享，并将该提取的特征数据与用于各种参考内容的提取的特征数据的数据库进行比较。当要共享的内容与数据库中的参考内容匹配时，可以简单地拒绝共享，或者可以检查与参考内容相关联的权限以便于确定授权。

6. 发明申请

US20120151247A1 Dynamic Fault Detection and Repair in a Data Communications Mechanism 有权
标题翻译：数据通信机制中的动态故障检测与修复
公开(公告)号：US20120151247A1
公开(公告)日：2012-06-14
申请号：US13159580
申请日：2011-06-14
申请人： Frank D. Ferraiolo , William R. Kelly , Robert J. Reese , Susan M. Rubow , Michael B. Spear
发明人： Frank D. Ferraiolo , William R. Kelly , Robert J. Reese , Susan M. Rubow , Michael B. Spear
IPC分类号： G06F11/20
CPC分类号： H04L45/28 , H04L1/22 , H04L1/24 , H04L7/0025 , H04L7/0337 , H04L25/14 , H04L45/22 , H04L69/40
摘要： A communications link of multiple parallel communications lines includes at least one redundant line. In a first aspect, the lines are periodically recalibrated one at a time while the others carry functional data. If a fault is detected, the faulty line is disabled and the remaining previously calibrated lines transmit functional data. In a second aspect, impending line malfunction is detected from anomalies during calibration. In a third aspect, line malfunction is detected from receiver circuit output by determining a logical lane upon which each detected error occurs, and by mapping the logical lane to a physical line currently carrying the logical lane data.
摘要翻译：多个并行通信线路的通信链路包括至少一个冗余线路。在第一方面，线路一次一个地重新校准，而其他线路携带功能数据。如果检测到故障，故障线路被禁用，其余的已校准线路传输功能数据。在第二方面，在校准期间从异常检测到即将发生的线路故障。在第三方面，通过确定发生每个检测到的错误的逻辑通道，并且将逻辑通道映射到当前携带逻辑车道数据的物理线路，从接收器电路输出检测线路故障。

7. 发明授权

US08139430B2 Power-on initialization and test for a cascade interconnect memory system 失效
标题翻译：级联互连存储器系统的上电初始化和测试
公开(公告)号：US08139430B2
公开(公告)日：2012-03-20
申请号：US12166139
申请日：2008-07-01
申请人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
发明人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
IPC分类号： G11C7/10 , G11C7/18
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.
摘要翻译：用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。该接口可在SBC模式和高速模式下工作。存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。

8. 发明授权

US08082475B2 Enhanced microprocessor interconnect with bit shadowing 有权
标题翻译：增强的微处理器互连与位阴影
公开(公告)号：US08082475B2
公开(公告)日：2011-12-20
申请号：US12165848
申请日：2008-07-01
申请人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
发明人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
IPC分类号： G06F11/14 , G06F11/30
CPC分类号： G06F11/2007 , G06F11/0724 , G06F11/076 , H04L1/20
摘要： Shadow selection logic is used to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. In addition shadow compare logic is used to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
摘要翻译：阴影选择逻辑用于选择驱动程序位位置作为阴影驱动程序值，线路驱动程序可以在总线的单独链路段上传输所选驱动程序位位置和阴影驱动程序值的数据。此外，阴影比较逻辑用于将选定的接收值与来自总线的阴影接收值进行比较，并根据比较不匹配识别错误比较，并且阴影计数器计数误差相对于总线错误率的速率经过一段时间。响应于在总线错误率的预定义阈值内的错误比较的速率来识别有缺陷的链路段。

9. 发明申请

US20100005202A1 DYNAMIC SEGMENT SPARING AND REPAIR IN A MEMORY SYSTEM 失效
标题翻译：动态部分在记忆系统中的分配和修复
公开(公告)号：US20100005202A1
公开(公告)日：2010-01-07
申请号：US12165809
申请日：2008-07-01
申请人： Frank D. Ferraiolo , Ravi K. Arimilli , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
发明人： Frank D. Ferraiolo , Ravi K. Arimilli , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
IPC分类号： G06F3/00
CPC分类号： G06F13/4243 , G06F11/2007 , G06F11/2017 , Y02D10/14 , Y02D10/151
摘要： A communication interface device, system, method, and design structure for providing dynamic segment sparing and repair in a memory system. The communication interface device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.
摘要翻译：用于在存储器系统中提供动态段保存和修复的通信接口设备，系统，方法和设计结构。通信接口装置包括驱动侧切换逻辑，包括驱动器多路复用器，用于选择用于在总线的链路段上发送的驱动器数据，以及包括接收机多路复用器的接收侧切换逻辑，以从总线的链路段选择接收的数据。该总线包括多个数据链路段，一个时钟链路段，以及由驱动器侧切换逻辑和接收侧切换逻辑选择的至少两个备用链路段，用于替换一个或多个数据链路段和时钟链路段。

10. 发明申请

US20090023124A1 Software Application System as an Efficient Client or Case Management Tool 审中-公开
标题翻译：软件应用系统作为高效的客户端或案例管理工具
公开(公告)号：US20090023124A1
公开(公告)日：2009-01-22
申请号：US12173523
申请日：2008-07-15
申请人： Dwayne E. Towell , Gideon P. Botha , Robert J. Reese
发明人： Dwayne E. Towell , Gideon P. Botha , Robert J. Reese
IPC分类号： G09B5/00
CPC分类号： G06Q10/10 , G06Q10/06 , G06Q50/20
摘要： A web application that facilitates the interaction between an educational institution and its members for the purpose of assisting a student in need is described. The application provides an accessible and user-friendly system for members of an educational institution to provide and gather information. The application may perform various functions that allow rapid and efficient transmission of information regarding a student in need so that those needs may be addressed.
摘要翻译：描述了一种促进教育机构与其成员之间的交互以帮助需要帮助的学生的网络应用程序。该应用程序为教育机构的成员提供可访问和用户友好的系统，以提供和收集信息。该应用可以执行各种功能，其允许快速且有效地传输关于需要的学生的信息，从而可以解决这些需求。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式