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1. 发明授权

US5752269A Pipelined microprocessor that pipelines memory requests to an external memory 失效
标题翻译：流水线的微处理器，将存储器请求管理到外部存储器
公开(公告)号：US5752269A
公开(公告)日：1998-05-12
申请号：US451150
申请日：1995-05-26
申请人： Robert J. Divivier , Ralph Haines , Mario D. Nemirovsky , Alexander Perez
发明人： Robert J. Divivier , Ralph Haines , Mario D. Nemirovsky , Alexander Perez
IPC分类号： G06F9/312 , G06F12/02
CPC分类号： G06F9/30043
摘要： Memory requests are pipelined to an external memory by forming a memory address during the same clock cycle that the associated instruction is executed, issuing a ready signal during the clock cycle that precedes the clock cycle in which information is output from an external memory, and directing information received from the external memory to a register file during the same clock cycle that the information is received. In addition, when an instruction requires the information that was requested by the previous instruction, the information is directed to an arithmetic logic unit (ALU) during the same clock cycle that the information is received. As a result, the cycle time required to retrieve information stored in a DRAM can be substantially reduced.
摘要翻译：存储器请求通过在与执行相关联的指令相同的时钟周期内形成存储器地址而被流水线地发送到外部存储器，在从外部存储器输出信息的时钟周期之前的时钟周期期间发出就绪信号，并且引导在接收信息的相同时钟周期内从外部存储器接收的信息到寄存器文件。此外，当指令需要由先前指令请求的信息时，在接收信息的相同时钟周期内，信息被引导到算术逻辑单元（ALU）。结果，可以显着地减少检索存储在DRAM中的信息所需的周期时间。

2. 发明授权

US07058070B2 Back pressure control system for network switch port 有权
标题翻译：网络交换机端口背压控制系统
公开(公告)号：US07058070B2
公开(公告)日：2006-06-06
申请号：US09847079
申请日：2001-05-01
申请人： Toan D. Tran , Robert J. Divivier
发明人： Toan D. Tran , Robert J. Divivier
IPC分类号： H04L12/28
CPC分类号： H04L12/5601 , H04L47/24 , H04L47/29 , H04L47/32 , H04L49/608 , H04L49/90 , H04L49/9084 , H04L2012/5635 , H04L2012/5679 , H04L2012/5681
摘要： A network switch port includes a cell memory, a queuing system, a data path controller and an output buffer. The data path controller stores incoming cells derived from network data transmissions in the cell memory. The queuing system generates the cell memory address of each stored cell when the cell is to be forwarded from the cell memory, and the data path controller appends the cell memory address of that cell to a linked list of addresses of cells to be forwarded from the memory. When the linked list is not empty, the data path controller forwards cells from the cell memory to the output buffer in the order that their cell memory addresses were appended to the linked list. The output buffer stores and then sequentially forwards the cells outward from the switch port to a receiving network component which store them in a cell buffer until it can forward them elsewhere. The receiving network component produces a multiple bit back pressure data indicating how much of its cell buffer is currently filled with cells. Depending on the fill amount the back pressure data indicates, the output buffer either halts or continues to forward cells to the receiving network component, and either halts or continues allowing the data path controller to forward cells from the cell memory to the output buffer.
摘要翻译：网络交换机端口包括小区存储器，排队系统，数据路径控制器和输出缓冲器。数据路径控制器将从网络数据传输导出的传入单元存储在单元存储器中。当小区从小区存储器转发时，排队系统生成每个存储的小区的小区存储器地址，并且数据路径控制器将该小区的小区存储器地址附加到要从其发送的小区地址的链表记忆。当链表不为空时，数据路径控制器将单元存储器的单元按照它们的单元存储器地址附加到链表的顺序将单元从单元存储器转发到输出缓冲器。输出缓冲器存储然后顺序地将单元从交换机端口向外转发到接收网络组件，该接收网络组件将它们存储在单元缓冲器中，直到其可以在其他地方转发。接收网络组件产生指示其小区缓冲器当前充满小区的多位背压数据。取决于背压数据指示的填充量，输出缓冲器停止或继续将单元转发到接收网络组件，并且停止或继续允许数据路径控制器将单元从单元存储器转发到输出缓冲器。

3. 发明授权

US06687781B2 Fair weighted queuing bandwidth allocation system for network switch port 有权
标题翻译：网络交换机端口的公平加权排队带宽分配系统
公开(公告)号：US06687781B2
公开(公告)日：2004-02-03
申请号：US09847078
申请日：2001-05-01
申请人： John M. Wynne , Robert J. Divivier
发明人： John M. Wynne , Robert J. Divivier
IPC分类号： G06F1300
CPC分类号： H04L47/623 , H04L47/50 , H04L47/525
摘要： A traffic manager for a network switch port stores incoming cells in a cell memory and later forwards them out of the cell memory and the switch port. Each cell is assigned to one of several flow queues and each flow queue has an assigned minimum forwarding bandwidth with which cells of that flow queue must be forwarded from the cell memory and has an assigned maximum bandwidth with which cells of that flow queue may be forwarded. When any flow queue is active (i.e., when it has cells currently stored in the cell memory), the traffic manager allocates a sufficient amount of the switch port's available cell forwarding bandwidth to each active flow queue so that cells of that flow queue are forwarded with at least the flow queue's assigned minimum bandwidth. Each flow queue also has an assigned forwarding weight, and the traffic manager also dynamically allocates a portion of the switch port's excess forwarding bandwidth, above that needed to accommodate each active flow queue's minimum bandwidth, among all active flow queues in relative proportion to each active flow queue's assigned forwarding weight. Thus the actual forwarding bandwidth allocated to each active flow queue is the sum of its assigned minimum forwarding bandwidth and its allocated portion of excess bandwidth. However the traffic manager limits the actual forwarding bandwidth allocated to any one flow queue so that it does not exceed the flow queue's assigned maximum forwarding bandwidth.
摘要翻译：网络交换机端口的流量管理器将进入的单元存储在单元存储器中，然后将其转发出单元存储器和交换机端口。每个小区被分配到几个流队列中的一个，并且每个流队列具有分配的最小转发带宽，该流队列的小区必须从小区存储器转发，并且具有分配的最大带宽，该流队列的小区可以被转发。当任何流队列处于活动状态时（即，当其存在当前存储在单元存储器中的单元）时，流量管理器为每个活动流队列分配足够量的交换机端口的可用小区转发带宽，使得该流队列的小区被转发至少具有流队列分配的最小带宽。每个流队列还具有分配的转发权重，并且流量管理器还在所有活动流队列中与每个活动相对比例动态地分配交换机端口的超出转发带宽的一部分，高于满足每个活动流队列的最小带宽所需的超出转发带宽流队列的转发权重。因此，分配给每个活动流队列的实际转发带宽是其分配的最小转发带宽与其分配的超额带宽部分的总和。但是，流量管理器限制分配给任何一个流队列的实际转发带宽，使其不超过流队列分配的最大转发带宽。

4. 发明授权

US06212181B1 Method for using the departure queue memory bandwidth to support additional cell arrivals in an ATM switch 有权
标题翻译：使用离开队列存储器带宽来支持ATM交换机中附加小区到达的方法
公开(公告)号：US06212181B1
公开(公告)日：2001-04-03
申请号：US09277657
申请日：1999-03-26
申请人： Robert J. Divivier , Christopher B. Bergen , Gary S. Goldman
发明人： Robert J. Divivier , Christopher B. Bergen , Gary S. Goldman
IPC分类号： H04L1250
CPC分类号： H04L49/3081 , H04L2012/5651 , H04L2012/5679 , H04L2012/5681 , H04Q11/0478
摘要： A system and method for assigning departure timeslots to arrival data in an ATM switch is described. The departure timeslots are assigned to arrival data when no departure data is pending or when arrival data has a higher priority than pending departure data.
摘要翻译：描述用于将出发时隙分配到ATM交换机中到达数据的系统和方法。当没有出发数据未决或到达数据的优先级高于待处理出发数据时，出发时间段被分配到到达数据。

5. 发明授权

US06618382B1 Auto early packet discard (EPD) mechanism for automatically enabling EPD on an asynchronous transfer mode (ATM) network 有权
标题翻译：自动早期分组丢弃（EPD）机制，用于在异步传输模式（ATM）网络上自动启用EPD
公开(公告)号：US06618382B1
公开(公告)日：2003-09-09
申请号：US09250972
申请日：1999-02-16
申请人： Robert J. Divivier , Christopher D. Bergen
发明人： Robert J. Divivier , Christopher D. Bergen
IPC分类号： H04L1250
CPC分类号： H04L47/32 , H04L12/5601 , H04L2012/5648 , H04L2012/5658 , H04L2012/5667
摘要： A method for automatic early packet discard mode enabling early packet discard on a cell switching network is disclosed. The method includes the steps of counting every non-end of the frame data cell that arrives on a network connection, comparing the number of non-end of the frame data cell to a predetermined threshold value to determine whether the traffic arriving on the network connection is a frame based traffic and enabling early packet discard if the traffic is frame based.
摘要翻译：公开了一种能够在小区交换网络上实现早期分组丢弃的自动早期分组丢弃模式的方法。该方法包括以下步骤：对到达网络连接的帧数据单元的每个非终端进行计数，将帧数据单元的非端数与预定阈值进行比较，以确定到达网络连接的流量是基于帧的业务，并且如果业务是基于帧的，则能够实现早期分组丢弃。

6. 发明授权

US06598132B2 Buffer manager for network switch port 有权
公开(公告)号：US06598132B2
公开(公告)日：2003-07-22
申请号：US09908616
申请日：2001-07-18
申请人： Toan D. Tran , Robert J. Divivier , Siyad Ma
发明人： Toan D. Tran , Robert J. Divivier , Siyad Ma
IPC分类号： G06F1200
CPC分类号： H04L49/901 , H04L49/254 , H04L49/3027 , H04L49/3045 , H04L49/90 , H04L49/9094
摘要： A traffic manager for a network switch port includes a buffer memory and a buffer manager for writing incoming cells into the buffer memory and for thereafter reading the cells out of the buffer memory and forwarding them. The traffic manager also includes a queue manager for determining an order in which the buffer manager is to forward a set of cells stored in the buffer memory. The queue manager supplies the buffer manager with a sequence of pointers, each pointer referencing a separate cell of the set of cells, with the sequence of pointers being ordered to indicate an order in which the buffer manager is to forward the set of cells. After receiving the pointer sequence, the buffer manager changes the order of pointers in the pointer sequence to optimize a rate at which it can read the cells out of the buffer memory. The buffer manager reads the cells out of the buffer memory in an order indicated by the changed pointer sequence and thereafter forwards the cells read out of the buffer memory in the order in which the queue manager determined the cells are to be forwarded.

7. 发明授权

US07181485B1 Variably delayable transmission of packets between independently clocked source, intermediate, and destination circuits while maintaining orderly and timely processing in one or both of the intermediate and destination circuits 有权
公开(公告)号：US07181485B1
公开(公告)日：2007-02-20
申请号：US09997507
申请日：2001-11-26
申请人： Onchuen (Daryn) Lau , Matthew D. Ornes , Chris D. Bergen , Robert J. Divivier , Gene K. Chui , Christopher I. W. Norrie , King-Shing (Frank) Chui
发明人： Onchuen (Daryn) Lau , Matthew D. Ornes , Chris D. Bergen , Robert J. Divivier , Gene K. Chui , Christopher I. W. Norrie , King-Shing (Frank) Chui
IPC分类号： G06F15/16
CPC分类号： G06F1/14 , H04L2012/5674
摘要： In a system having independently-clocked job-performing circuits (e.g., payload processors) and independently-clocked job-ordering circuits (e.g., request and payload suppliers), coordinating mechanisms are provided for coordinating exchanges between the independently-clocked circuits. The coordinating mechanisms include those that use transmitted time-stamps for scheduling contention-free performances within the job-performing circuits of requested jobs. The coordinating mechanisms additionally or alternatively include static and dynamic rate constraining means that are configured to prevent a faster-clocked one of the independently-clocked circuits from overwhelming a more slowly-clocked other of the independently-clocked circuits. In one implementation, independently-clocked telecommunication-shelves house a distributed set of line cards and switch cards. An asynchronous interconnect is provided between the independently-clocked shelves for carrying job requests and payload data between the distributed line cards and the distributed switch cards. The multi-shelf system is scalable and robust because additional or replacement line and switch cards may be inserted into one or another of the independently-clocked shelves as desired and because a unified clock-tree is not needed for synchronizing activities within the interconnected, but independently clocked shelves.

8. 发明授权

US07079485B1 Multiservice switching system with distributed switch fabric 失效
标题翻译：具有分布式交换矩阵的多业务交换系统
公开(公告)号：US07079485B1
公开(公告)日：2006-07-18
申请号：US09847711
申请日：2001-05-01
申请人： Onchuen (Daryn) Lau , Chris D. Bergen , Robert J. Divivier , Gene K. Chui , Christopher I. W. Norrie , Matthew D. Ornes , King-Shing (Frank) Chui
发明人： Onchuen (Daryn) Lau , Chris D. Bergen , Robert J. Divivier , Gene K. Chui , Christopher I. W. Norrie , Matthew D. Ornes , King-Shing (Frank) Chui
IPC分类号： H04L12/56 , H04J14/08
CPC分类号： H04L49/45 , H04L49/201 , H04L49/3045 , H04L49/357 , H04L49/503 , H04L2012/5618
摘要： A digital switching system comprises: (a) a line card layer containing a plurality of real or virtual line cards; (b) a switch card layer containing a plurality of real or virtual switch cards; and (c) an interface layer interposed between the line card layer and the switch card layer for providing serialization support services so that one or more of the line cards and switch cards can be operatively and conveniently disposed in a first shelf or on a first backplane that is spaced apart from a second shelf or from a second backplane supporting others of the line cards and/or switch cards. Such an arrangement allows for scalable expansion of the switching system in terms of number of lines served and/or transmission rates served. The flexibility of the system is owed in part to payload data being carried within payload-carrying regions of so-called ZCell signals as the payload data moves between the line card layer and the switch fabric layer.
摘要翻译：数字交换系统包括：（a）包含多个真实或虚拟线路卡的线路卡层; （b）包含多个实际或虚拟交换卡的交换机卡层; 以及（c）插入在线卡层和开关卡层之间的界面层，用于提供串行化支持服务，使得线卡和开关卡中的一个或多个可以可操作地和方便地设置在第一架或第一背板其与第二搁架间隔开，或者从支撑其他线路卡和/或开关卡的第二背板间隔开。这样的布置允许在服务的线路数量和/或传输速率方面可以扩展交换系统。当有效载荷数据在线路卡层和交换结构层之间移动时，系统的灵活性部分归因于在所谓的ZCell信号的有效负载区域内承载的有效载荷数据。

9. 发明授权

US07058057B2 Network switch port traffic manager having configurable packet and cell servicing 有权
公开(公告)号：US07058057B2
公开(公告)日：2006-06-06
申请号：US09847077
申请日：2001-05-01
申请人： David L. Dooley , Robert J. Divivier
发明人： David L. Dooley , Robert J. Divivier
IPC分类号： H04L12/28
CPC分类号： H04L47/10 , H04L12/5601 , H04L47/22 , H04L47/50 , H04L47/522 , H04L49/255 , H04L49/3081 , H04L2012/5651 , H04L2012/5652 , H04L2012/5679 , H04L2012/5681 , H04Q11/0478
摘要： An input or output switch port for a network switch converts each incoming packet into a cell sequence stores each cell in a cell memory. The switch port includes a traffic manager for queuing cells for departure from the cell memory and then signaling the cell memory to read out and forward cells in the order they are queued. The traffic manager selectively queues cells for departure on either a cell-by-cell or sequence-by-sequence basis. When cells are queued for departure on a cell-by-cell basis, cells of two or more sequences may be alternately read out and forwarded from the cell memory. Thus cells of different sequences may be interleaved with one another as they depart the cell memory. When a cell sequence is queued on a sequence-by-sequence basis all of its cells are read out of the cell memory and forwarded as a contiguous sequence and are not interleaved with cells of other sequences of the same departure queue. Each packet includes a flow identification number (FIN) value and the traffic manager determines from the packet's FIN whether to queue cell sequences derived from the packet on a cell-by-cell or sequence-by-sequence basis.

10. 发明授权

US06959002B2 Traffic manager for network switch port 有权
标题翻译：网络交换机端口的流量管理器
公开(公告)号：US06959002B2
公开(公告)日：2005-10-25
申请号：US09908614
申请日：2001-07-18
申请人： John M. Wynne , David L. Dooley , Robert J. Divivier
发明人： John M. Wynne , David L. Dooley , Robert J. Divivier
IPC分类号： H04L12/56 , H04Q11/04 , H04L12/28 , H04L12/54
CPC分类号： H04L49/3081 , H04L49/255 , H04L2012/5631 , H04L2012/5679 , H04L2012/5681 , H04Q11/0478
摘要： A traffic manager for a network switch input or output port stores incoming cells in a cell memory and later sends each cell out of its cell memory toward one of a set of forwarding resources such as, for example, another switch port or an output bus. Data in each cell references the particular forwarding resource to receive the cell. Each cell is assigned to one of several flow queues such that all cells assigned to the same flow queue are to be sent to the same forwarding resource. The traffic manager maintains a separate virtual output queue (VOQ) associated with each forwarding resource and periodically loads a flow queue (FQ) number identifying each flow queue into the VOQ associated with the forwarding resource that is to receive the cells assigned to that FQ. The traffic manager also periodically shifts an FQ ID out of each non-empty VOQ and forwards the longest-stored cell assigned to that FQ from the cell memory toward its intended forwarding resource. The traffic manager separately determines the rates at which it loads FQ IDs into VOQs and the rates at which it shifts FQ IDs out of each non-empty VOQ. Thus the traffic manager is able to separately control the rate at which cells of each flow queue are forwarded and the rate at which each forwarding resource receives cells.
摘要翻译：用于网络交换机输入或输出端口的流量管理器将进入的单元存储在单元存储器中，并且随后将每个单元从其单元存储器发送到一组转发资源中的一个，例如另一个开关端口或输出总线。每个单元中的数据引用特定的转发资源来接收单元。每个小区被分配给几个流队列中的一个，使得分配给相同流队列的所有小区将被发送到相同的转发资源。流量管理器维护与每个转发资源相关联的单独的虚拟输出队列（VOQ），并且周期性地将识别每个流队列的流队列（FQ）加载到与要接收分配给该FQ的小区的转发资源相关联的VOQ中。流量管理器还周期地从每个非空VOQ移出FQ ID，并将分配给该FQ的最长存储单元从单元存储器转发到其预期的转发资源。流量管理器单独确定将FQ ID加载到VOQ中的速率以及从每个非空VOQ中移除FQ ID的速率。因此，流量管理器能够分别控制每个流队列的小区被转发的速率以及每个转发资源接收小区的速率。

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