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1. 发明申请

US20130086570A1 LINKING CODE FOR AN ENHANCED APPLICATION BINARY INTERFACE (ABI) WITH DECODE TIME INSTRUCTION OPTIMIZATION 失效
标题翻译：链接代码用于增强应用二进制接口（ABI）与解码时间指令优化
公开(公告)号：US20130086570A1
公开(公告)日：2013-04-04
申请号：US13251793
申请日：2011-10-03
申请人： Robert J. Blainey , Michael K. Gschwind , James L. McInnes , Michael R. Meissner , Steven J. Munroe
发明人： Robert J. Blainey , Michael K. Gschwind , James L. McInnes , Michael R. Meissner , Steven J. Munroe
IPC分类号： G06F9/44
CPC分类号： G06F8/54 , G06F9/3017 , G06F9/342
摘要： A code sequence made up multiple instructions and specifying an offset from a base address is identified in an object file. The offset from the base address corresponds to an offset location in a memory configured for storing an address of a variable or data. The identified code sequence is configured to perform a memory reference function or a memory address computation function. It is determined that the offset location is within a specified distance of the base address and that a replacement of the identified code sequence with a replacement code sequence will not alter program semantics. The identified code sequence in the object file is replaced with the replacement code sequence that includes a no-operation (NOP) instruction or having fewer instructions than the identified code sequence. Linked executable code is generated based on the object file and the linked executable code is emitted.
摘要翻译：在目标文件中标识由多个指令构成的代码序列并指定与基地址的偏移量。与基地址的偏移量对应于配置为存储变量或数据地址的存储器中的偏移位置。所识别的代码序列被配置为执行存储器引用功能或存储器地址计算功能。确定偏移位置在基地址的指定距离内，并且用替换代码序列替换所识别的代码序列将不会改变程序语义。目标文件中所识别的代码序列被替换为包含无操作（NOP）指令或具有比识别的代码序列少的指令的替换代码序列。链接的可执行代码是基于目标文件生成的，并且发送链接的可执行代码。

2. 发明授权

US08612959B2 Linking code for an enhanced application binary interface (ABI) with decode time instruction optimization 失效
公开(公告)号：US08612959B2
公开(公告)日：2013-12-17
申请号：US13251793
申请日：2011-10-03
申请人： Robert J. Blainey , Michael K. Gschwind , James L. McInnes , Michael R. Meissner , Steven J. Munroe
发明人： Robert J. Blainey , Michael K. Gschwind , James L. McInnes , Michael R. Meissner , Steven J. Munroe
IPC分类号： G06F9/44
CPC分类号： G06F8/54 , G06F9/3017 , G06F9/342
摘要： A code sequence made up multiple instructions and specifying an offset from a base address is identified in an object file. The offset from the base address corresponds to an offset location in a memory configured for storing an address of a variable or data. The identified code sequence is configured to perform a memory reference function or a memory address computation function. It is determined that the offset location is within a specified distance of the base address and that a replacement of the identified code sequence with a replacement code sequence will not alter program semantics. The identified code sequence in the object file is replaced with the replacement code sequence that includes a no-operation (NOP) instruction or having fewer instructions than the identified code sequence. Linked executable code is generated based on the object file and the linked executable code is emitted.

3. 发明授权

US08607211B2 Linking code for an enhanced application binary interface (ABI) with decode time instruction optimization 失效
标题翻译：链接代码用于增强应用二进制接口（ABI）与解码时间指令优化
公开(公告)号：US08607211B2
公开(公告)日：2013-12-10
申请号：US13458108
申请日：2012-04-27
申请人： Robert J. Blainey , Michael K. Gschwind , James L. McInnes , Michael R. Meissner , Steven J. Munroe
发明人： Robert J. Blainey , Michael K. Gschwind , James L. McInnes , Michael R. Meissner , Steven J. Munroe
IPC分类号： G06F9/44
CPC分类号： G06F8/54 , G06F9/3017 , G06F9/342
摘要： A code sequence made up multiple instructions and specifying an offset from a base address is identified in an object file. The offset from the base address corresponds to an offset location in a memory configured for storing an address of a variable or data. The identified code sequence is configured to perform a memory reference function or a memory address computation function. It is determined that the offset location is within a specified distance of the base address and that a replacement of the identified code sequence with a replacement code sequence will not alter program semantics. The identified code sequence in the object file is replaced with the replacement code sequence that includes a no-operation (NOP) instruction or having fewer instructions than the identified code sequence. Linked executable code is generated based on the object file and the linked executable code is emitted.
摘要翻译：在目标文件中标识由多个指令构成的代码序列并指定与基地址的偏移量。与基地址的偏移量对应于配置为存储变量或数据地址的存储器中的偏移位置。所识别的代码序列被配置为执行存储器引用功能或存储器地址计算功能。确定偏移位置在基地址的指定距离内，并且用替换代码序列替换所识别的代码序列将不会改变程序语义。目标文件中所识别的代码序列被替换为包含无操作（NOP）指令或具有比识别的代码序列少的指令的替换代码序列。链接的可执行代码是基于目标文件生成的，并且发送链接的可执行代码。

4. 发明申请

US20130086338A1 LINKING CODE FOR AN ENHANCED APPLICATION BINARY INTERFACE (ABI) WITH DECODE TIME INSTRUCTION OPTIMIZATION 失效
公开(公告)号：US20130086338A1
公开(公告)日：2013-04-04
申请号：US13458108
申请日：2012-04-27
申请人： Robert J. Blainey , Michael K. Gschwind , James L. McInnes , Michael R. Meissner , Steven J. Munroe
发明人： Robert J. Blainey , Michael K. Gschwind , James L. McInnes , Michael R. Meissner , Steven J. Munroe
IPC分类号： G06F12/02
CPC分类号： G06F8/54 , G06F9/3017 , G06F9/342
摘要： A code sequence made up multiple instructions and specifying an offset from a base address is identified in an object file. The offset from the base address corresponds to an offset location in a memory configured for storing an address of a variable or data. The identified code sequence is configured to perform a memory reference function or a memory address computation function. It is determined that the offset location is within a specified distance of the base address and that a replacement of the identified code sequence with a replacement code sequence will not alter program semantics. The identified code sequence in the object file is replaced with the replacement code sequence that includes a no-operation (NOP) instruction or having fewer instructions than the identified code sequence. Linked executable code is generated based on the object file and the linked executable code is emitted.

5. 发明授权

US08615746B2 Compiling code for an enhanced application binary interface (ABI) with decode time instruction optimization 失效
标题翻译：使用解码时间指令优化编译用于增强应用二进制接口（ABI）的代码
公开(公告)号：US08615746B2
公开(公告)日：2013-12-24
申请号：US13459594
申请日：2012-04-30
申请人： Robert J. Blainey , Michael K. Gschwind , James L. McInnes , Steven J. Munroe
发明人： Robert J. Blainey , Michael K. Gschwind , James L. McInnes , Steven J. Munroe
IPC分类号： G06F9/45
CPC分类号： G06F8/41 , G06F8/443 , G06F8/54
摘要： Compiling code for an enhanced application binary interface (ABI) including identifying, by a computer, a code sequence configured to perform a variable address reference table function including an access to a variable at an offset outside of a location in a variable address reference table. The code sequence includes an internal representation (IR) of a first instruction and an IR of a second instruction. The second instruction is dependent on the first instruction. A scheduler cost function associated with at least one of the IR of the first instruction and the IR of the second instruction is modified. The modifying includes generating a modified scheduler cost function that is configured to place the first instruction next to the second instruction. An object file is generated responsive to the modified scheduler cost function. The object file includes the first instruction placed next to the second instruction. The object file is emitted.
摘要翻译：编译用于增强型应用二进制接口（ABI）的代码，包括由计算机识别被配置为执行可变地址参考表函数的代码序列，所述变量地址参考表函数包括对可变地址参考表中位置之外的偏移量的变量的访问。代码序列包括第一指令的内部表示（IR）和第二指令的IR。第二条指令取决于第一条指令。与第一指令的IR和第二指令的IR中的至少一个相关联的调度器成本函数被修改。修改包括生成被配置为将第一指令放置在第二指令旁边的修改的调度器成本函数。响应于修改的调度器成本函数生成对象文件。目标文件包括放置在第二条指令旁边的第一条指令。目标文件被发出。

6. 发明申请

US20130086369A1 COMPILING CODE FOR AN ENHANCED APPLICATION BINARY INTERFACE (ABI) WITH DECODE TIME INSTRUCTION OPTIMIZATION 失效
标题翻译：用于加强应用二进制接口（ABI）的编码与解码时间指令优化
公开(公告)号：US20130086369A1
公开(公告)日：2013-04-04
申请号：US13459594
申请日：2012-04-30
申请人： Robert J. Blainey , Michael K. Gschwind , James L. McInnes , Steven J. Munroe
发明人： Robert J. Blainey , Michael K. Gschwind , James L. McInnes , Steven J. Munroe
IPC分类号： G06F9/318
CPC分类号： G06F8/41 , G06F8/443 , G06F8/54
摘要： Compiling code for an enhanced application binary interface (ABI) including identifying, by a computer, a code sequence configured to perform a variable address reference table function including an access to a variable at an offset outside of a location in a variable address reference table. The code sequence includes an internal representation (IR) of a first instruction and an IR of a second instruction. The second instruction is dependent on the first instruction. A scheduler cost function associated with at least one of the IR of the first instruction and the IR of the second instruction is modified. The modifying includes generating a modified scheduler cost function that is configured to place the first instruction next to the second instruction. An object file is generated responsive to the modified scheduler cost function. The object file includes the first instruction placed next to the second instruction. The object file is emitted.
摘要翻译：编译用于增强型应用二进制接口（ABI）的代码，包括由计算机识别被配置为执行可变地址参考表函数的代码序列，所述变量地址参考表函数包括对可变地址参考表中位置之外的偏移量的变量的访问。代码序列包括第一指令的内部表示（IR）和第二指令的IR。第二条指令取决于第一条指令。与第一指令的IR和第二指令的IR中的至少一个相关联的调度器成本函数被修改。修改包括生成被配置为将第一指令放置在第二指令旁边的修改的调度器成本函数。响应于修改的调度器成本函数生成对象文件。目标文件包括放置在第二条指令旁边的第一条指令。目标文件被发出。

7. 发明申请

US20130086563A1 COMPILING CODE FOR AN ENHANCED APPLICATION BINARY INTERFACE (ABI) WITH DECODE TIME INSTRUCTION OPTIMIZATION 失效
标题翻译：用于加强应用二进制接口（ABI）的编码与解码时间指令优化
公开(公告)号：US20130086563A1
公开(公告)日：2013-04-04
申请号：US13251798
申请日：2011-10-03
申请人： Robert J. Blainey , Michael Gschwind , James L. McInnes , Steven J. Munroe
发明人： Robert J. Blainey , Michael Gschwind , James L. McInnes , Steven J. Munroe
IPC分类号： G06F9/45
CPC分类号： G06F8/41 , G06F8/443 , G06F8/54
摘要： A code sequence made up multiple instructions and specifying an offset from a base address is identified in an object file. The offset from the base address corresponds to an offset location in a memory configured for storing an address of a variable or data. The identified code sequence is configured to perform a memory reference function or a memory address computation function. It is determined that the offset location is within a specified distance of the base address and that a replacement of the identified code sequence with a replacement code sequence will not alter program semantics. The identified code sequence in the object file is replaced with the replacement code sequence that includes a no-operation (NOP) instruction or having fewer instructions than the identified code sequence. Linked executable code is generated based on the object file and the linked executable code is emitted.
摘要翻译：在目标文件中标识由多个指令构成的代码序列并指定与基地址的偏移量。与基地址的偏移量对应于配置为存储变量或数据地址的存储器中的偏移位置。所识别的代码序列被配置为执行存储器引用功能或存储器地址计算功能。确定偏移位置在基地址的指定距离内，并且用替换代码序列替换所识别的代码序列将不会改变程序语义。目标文件中所识别的代码序列被替换为包含无操作（NOP）指令或具有比识别的代码序列少的指令的替换代码序列。链接的可执行代码是基于目标文件生成的，并且发送链接的可执行代码。

8. 发明授权

US08615745B2 Compiling code for an enhanced application binary interface (ABI) with decode time instruction optimization 失效
标题翻译：使用解码时间指令优化编译用于增强应用二进制接口（ABI）的代码
公开(公告)号：US08615745B2
公开(公告)日：2013-12-24
申请号：US13251798
申请日：2011-10-03
申请人： Robert J. Blainey , Michael Gschwind , James L. McInnes , Steven J. Munroe
发明人： Robert J. Blainey , Michael Gschwind , James L. McInnes , Steven J. Munroe
IPC分类号： G06F9/45
CPC分类号： G06F8/41 , G06F8/443 , G06F8/54
摘要： A code sequence made up multiple instructions and specifying an offset from a base address is identified in an object file. The offset from the base address corresponds to an offset location in a memory configured for storing an address of a variable or data. The identified code sequence is configured to perform a memory reference function or a memory address computation function. It is determined that the offset location is within a specified distance of the base address and that a replacement of the identified code sequence with a replacement code sequence will not alter program semantics. The identified code sequence in the object file is replaced with the replacement code sequence that includes a no-operation (NOP) instruction or having fewer instructions than the identified code sequence. Linked executable code is generated based on the object file and the linked executable code is emitted.
摘要翻译：在目标文件中标识由多个指令构成的代码序列并指定与基地址的偏移量。与基地址的偏移量对应于配置为存储变量或数据地址的存储器中的偏移位置。所识别的代码序列被配置为执行存储器引用功能或存储器地址计算功能。确定偏移位置在基地址的指定距离内，并且用替换代码序列替换所识别的代码序列将不会改变程序语义。目标文件中所识别的代码序列被替换为包含无操作（NOP）指令或具有比识别的代码序列少的指令的替换代码序列。链接的可执行代码是基于目标文件生成的，并且发送链接的可执行代码。

9. 发明申请

US20090064152A1 SYSTEMS, METHODS AND COMPUTER PRODUCTS FOR CROSS-THREAD SCHEDULING 有权
标题翻译：用于交叉螺纹调度的系统，方法和计算机产品
公开(公告)号：US20090064152A1
公开(公告)日：2009-03-05
申请号：US11847556
申请日：2007-08-30
申请人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels , James L. McInnes , Mark P. Mendell
发明人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels , James L. McInnes , Mark P. Mendell
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F8/445 , G06F9/3885
摘要： Systems, methods and computer products for cross-thread scheduling. Exemplary embodiments include a cross thread scheduling method for compiling code, the method including scheduling a scheduling unit with a scheduler sub-operation in response to the scheduling unit being in a non-multithreaded part of the code and scheduling the scheduling unit with a cross-thread scheduler sub-operation in response to the scheduling unit being in a multithreaded part of the code.
摘要翻译：用于跨线程调度的系统，方法和计算机产品。示例性实施例包括用于编译代码的交叉线程调度方法，所述方法包括：响应于所述调度单元处于所述代码的非多线程部分中的调度器子操作来调度调度单元，并且调度所述调度单元，响应于调度单元处于代码的多线程部分中的线程调度器子操作。

10. 发明授权

US08413127B2 Fine-grained software-directed data prefetching using integrated high-level and low-level code analysis optimizations 有权
标题翻译：使用集成的高级和低级代码分析优化进行细粒度的软件导向数据预取
公开(公告)号：US08413127B2
公开(公告)日：2013-04-02
申请号：US12644756
申请日：2009-12-22
申请人： Roch G. Archambault , Robert J. Blainey , Yaoqing Gao , Allan R. Martin , James L. McInnes , Francis Patrick O'Connell
发明人： Roch G. Archambault , Robert J. Blainey , Yaoqing Gao , Allan R. Martin , James L. McInnes , Francis Patrick O'Connell
IPC分类号： G06F9/44 , G06F9/45 , G06F9/30
CPC分类号： G06F8/4442
摘要： A mechanism for minimizing effective memory latency without unnecessary cost through fine-grained software-directed data prefetching using integrated high-level and low-level code analysis and optimizations is provided. The mechanism identifies and classifies streams, identifies data that is most likely to incur a cache miss, exploits effective hardware prefetching to determine the proper number of streams to be prefetched, exploits effective data prefetching on different types of streams in order to eliminate redundant prefetching and avoid cache pollution, and uses high-level transformations with integrated lower level cost analysis in the instruction scheduler to schedule prefetch instructions effectively.
摘要翻译：提供了一种通过使用集成高级和低级代码分析和优化的细粒度软件导向数据预取来最小化有效存储器延迟而不需要成本的机制。该机制识别和分类流，识别最可能引起缓存未命中的数据，利用有效的硬件预取来确定要预取的流的适当数量，利用不同类型的流上的有效数据预取，以消除冗余预取和避免高速缓存污染，并在指令调度程序中使用集成较低级别成本分析的高级转换，有效地调度预取指令。

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