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1. 发明授权

US08091073B2 Scaling instruction intervals to identify collection points for representative instruction traces 失效
标题翻译：缩放指令间隔以标识代表性指令轨迹的收集点
公开(公告)号：US08091073B2
公开(公告)日：2012-01-03
申请号：US11758031
申请日：2007-06-05
申请人： Robert H. Bell, Jr. , Wen-Tzer T. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
发明人： Robert H. Bell, Jr. , Wen-Tzer T. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
IPC分类号： G06F9/44
CPC分类号： G06F11/36
摘要： A method, system, and computer program product are provided for identifying instructions to obtain representative traces. A phase instruction budget is calculated for each phase in a set of phases. The phase instruction budget is based on a weight associated with each phase and a global instruction budget. A starting index and an ending index are identified for instructions within a set of intervals in each phase in order to meet the phase instruction budget for that phase, thereby forming a set of interval indices. A determination is made as to whether the instructions within the set of interval indices meet the global instruction budget. Responsive to the global instruction budget being met, the set of interval indices are output as collection points for the representative traces.
摘要翻译：提供方法，系统和计算机程序产品用于识别指令以获得代表性迹线。针对一组阶段中的每个阶段计算相位指令预算。相位指令预算基于与每个阶段相关联的权重和全局指令预算。为了满足该阶段的相位指令预算，为每个阶段的一组间隔内的指令识别开始索引和结束索引，从而形成一组间隔索引。确定区间指标集内的指令是否符合全球指令预算。响应于满足全球指令预算，间隔指数的集合作为代表性跟踪的收集点输出。

2. 发明申请

US20080307203A1 Scaling Instruction Intervals to Identify Collection Points for Representative Instruction Traces 失效
标题翻译：缩放指令间隔以识别代表性指令跟踪的收集点
公开(公告)号：US20080307203A1
公开(公告)日：2008-12-11
申请号：US11758031
申请日：2007-06-05
申请人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
发明人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
IPC分类号： G06F9/30
CPC分类号： G06F11/36
摘要： A method, system, and computer program product are provided for identifying instructions to obtain representative traces. A phase instruction budget is calculated for each phase in a set of phases. The phase instruction budget is based on a weight associated with each phase and a global instruction budget. A starting index and an ending index are identified for instructions within a set of intervals in each phase in order to meet the phase instruction budget for that phase, thereby forming a set of interval indices. A determination is made as to whether the instructions within the set of interval indices meet the global instruction budget. Responsive to the global instruction budget being met, the set of interval indices are output as collection points for the representative traces.
摘要翻译：提供方法，系统和计算机程序产品用于识别指令以获得代表性迹线。针对一组阶段中的每个阶段计算相位指令预算。相位指令预算基于与每个阶段相关联的权重和全局指令预算。为了满足该阶段的相位指令预算，为每个阶段的一组间隔内的指令识别开始索引和结束索引，从而形成一组间隔索引。确定区间指标集内的指令是否符合全球指令预算。响应于满足全球指令预算，间隔指数的集合作为代表性跟踪的收集点输出。

3. 发明申请

US20090183127A1 Method and Apparatus for Evaluating Integrated Circuit Design Performance Using Enhanced Basic Block Vectors that Include Data Dependent Information 有权
标题翻译：使用包含数据相关信息的增强型基本块向量来评估集成电路设计性能的方法和装置
公开(公告)号：US20090183127A1
公开(公告)日：2009-07-16
申请号：US11972747
申请日：2008-01-11
申请人： Robert H. Bell , Thomas W. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
发明人： Robert H. Bell , Thomas W. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A test system or simulator includes an IC benchmark software program that executes application software on a semiconductor die IC design model. The benchmark software includes trace, simulation point, clustering and other programs. IC designers utilize the benchmark software to evaluate the performance characteristics of IC designs with customer user software applications. The benchmark software generates basic block vectors BBVs from instruction traces of application software. The benchmark software analyzes data dependent information that it appends to BBVs to create enhanced BBVs or EBBVs. The benchmark software may graph the EBBV information in a cluster diagram and selects a subset of EBBVs as a representative sample for each program phase. Benchmarking software generates a reduced application software program from the representative EBBV samples. Designers use the test system with benchmarking software to evaluate IC design model modifications by using the representative reduced application software program.
摘要翻译：测试系统或模拟器包括在半导体芯片IC设计模型上执行应用软件的IC基准软件程序。基准软件包括跟踪，模拟点，聚类和其他程序。 IC设计人员利用基准软件来评估用户用户软件应用的IC设计的性能特征。基准软件从应用软件的指令轨迹生成基本块向量BBV。基准软件分析数据相关信息，它附加到BBV以创建增强型BBV或EBBV。基准软件可以在一个聚类图中绘制EBBV信息，并选择一个EBBV子集作为每个程序阶段的代表性样本。基准测试软件从代表性的EBBV样本中生成一个减少的应用软件程序。设计人员使用带有基准测试软件的测试系统，通过使用代表性的减少应用软件程序来评估IC设计模型修改。

4. 发明授权

US07844928B2 Method and apparatus for evaluating integrated circuit design performance using enhanced basic block vectors that include data dependent information 有权
标题翻译：使用包括数据相关信息的增强型基本块向量来评估集成电路设计性能的方法和装置
公开(公告)号：US07844928B2
公开(公告)日：2010-11-30
申请号：US11972747
申请日：2008-01-11
申请人： Robert H. Bell , Thomas W. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
发明人： Robert H. Bell , Thomas W. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A test system or simulator includes an IC benchmark software program that executes application software on a semiconductor die IC design model. The benchmark software includes trace, simulation point, clustering and other programs. IC designers utilize the benchmark software to evaluate the performance characteristics of IC designs with customer user software applications. The benchmark software generates basic block vectors BBVs from instruction traces of application software. The benchmark software analyzes data dependent information that it appends to BBVs to create enhanced BBVs or EBBVs. The benchmark software may graph the EBBV information in a cluster diagram and selects a subset of EBBVs as a representative sample for each program phase. Benchmarking software generates a reduced application software program from the representative EBBV samples. Designers use the test system with benchmarking software to evaluate IC design model modifications by using the representative reduced application software program.
摘要翻译：测试系统或模拟器包括在半导体芯片IC设计模型上执行应用软件的IC基准软件程序。基准软件包括跟踪，模拟点，聚类和其他程序。 IC设计人员利用基准软件来评估用户用户软件应用的IC设计的性能特征。基准软件从应用软件的指令轨迹生成基本块向量BBV。基准软件分析数据相关信息，它附加到BBV以创建增强型BBV或EBBV。基准软件可以在一个聚类图中绘制EBBV信息，并选择一个EBBV子集作为每个程序阶段的代表性样本。基准测试软件从代表性的EBBV样本中生成一个减少的应用软件程序。设计人员使用带有基准测试软件的测试系统，通过使用代表性的减少应用软件程序来评估IC设计模型修改。

5. 发明授权

US07392366B2 Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches 有权
标题翻译：多线程处理器中的自适应提取门控，提取控制和控制提取的方法
公开(公告)号：US07392366B2
公开(公告)日：2008-06-24
申请号：US11228781
申请日：2005-09-16
申请人： Pradip Bose , Alper Buyuktosunoglu , Richard J. Eickemeyer , Lee E. Eisen , Philip G. Emma , John B. Griswell , Zhigang Hu , Hung Q. Le , Douglas R. Logan , Balaram Sinharoy
发明人： Pradip Bose , Alper Buyuktosunoglu , Richard J. Eickemeyer , Lee E. Eisen , Philip G. Emma , John B. Griswell , Zhigang Hu , Hung Q. Le , Douglas R. Logan , Balaram Sinharoy
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3867
摘要： A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signs are monitored for downstream pipeline conditions indicating pipeline execution thread states. Instruction cache fetches are skipped for any thread that is incapable of receiving fetched cache contents, e.g., because the thread is full or stalled. Also, consecutive fetches may be selected for the same thread, e.g., on a branch mis-predict. Thus, the processor avoids wasting power on unnecessary or place keeper fetches.
摘要翻译：多线程处理器，用于多线程处理器的获取控制以及在多线程处理器中获取的方法。监视处理器事件和使用（EU）符号，用于指示管道执行线程状态的下游管道条件。对于不能接收获取的高速缓存内容的任何线程，例如由于线程已满或停顿，跳过指令高速缓存提取。此外，可以针对相同的线程选择连续的提取，例如在分支误预测中。因此，处理器避免浪费电力不必要的或放置保持器提取。

6. 发明授权

US5377336A Improved method to prefetch load instruction data 失效
标题翻译：改进预取加载指令数据的方法
公开(公告)号：US5377336A
公开(公告)日：1994-12-27
申请号：US920947
申请日：1992-07-28
申请人： Richard J. Eickemeyer , Stamatis Vassiliadis
发明人： Richard J. Eickemeyer , Stamatis Vassiliadis
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F9/383 , G06F9/3832 , G06F9/3844 , G06F9/3885
摘要： Described is a Load Unit for processing the data fetch in load instructions. The Load Unit predicts the address for the data fetch such that the fetch can occur earlier than in the typical load processing. By processing the fetch early, the normal cache access cycle can be eliminated reducing overall execution time. Cache misses can be processed in parallel with other execution thereby reducing the performance degradation of cache misses.
摘要翻译：描述了一种用于处理加载指令中的数据获取的加载单元。加载单元预测数据提取的地址，使得提取可以比典型的加载处理早。通过提前处理提取，可以消除正常的高速缓存访问周期，减少总体执行时间。可以与其他执行并行处理高速缓存未命中，从而降低高速缓存未命中的性能下降。

7. 发明授权

US07797521B2 Method, system, and computer program product for path-correlated indirect address predictions 有权
标题翻译：路径相关间接地址预测的方法，系统和计算机程序产品
公开(公告)号：US07797521B2
公开(公告)日：2010-09-14
申请号：US11734519
申请日：2007-04-12
申请人： Richard J. Eickemeyer , Michael K. Gschwind , Ravi Nair , Robert A. Philhower
发明人： Richard J. Eickemeyer , Michael K. Gschwind , Ravi Nair , Robert A. Philhower
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3848
摘要： A method, system, and computer program product are provided, for maintaining a path history register of register indirect branches. A set of bits is generated based on a set of target address bits using a hit selection and/or a hash function operation, and the generated set of bits is inserted into a path history register by shifting bits in the path history register and/or applying a hash operation, information corresponding to prior history is removed from the path history register, using a shift out operation and/or a hash operation. The path, history register is used to maintain a recent target, table and generate register-indirect branch target address predictions based on path history correlation between register-indirect branches captured by the path history register.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于维护寄存器间接分支的路径历史寄存器。使用命中选择和/或散列函数操作，基于一组目标地址位产生一组位，并且通过将路径历史寄存器中的位移位和/或将该生成的位组插入到路径历史寄存器中使用散列操作，使用移出操作和/或散列操作从路径历史寄存器中移除与先前历史相对应的信息。路径历史寄存器用于维护最近的目标，表格，并根据由路径历史寄存器捕获的寄存器间接分支之间的路径历史相关性生成寄存器间接分支目标地址预测。

8. 发明授权

US5459844A Predecode instruction compounding 失效
标题翻译：预解码指令复合
公开(公告)号：US5459844A
公开(公告)日：1995-10-17
申请号：US287435
申请日：1994-08-08
申请人： Richard J. Eickemeyer , Stamatis Vassiliadis , Bartholomew Blaner
发明人： Richard J. Eickemeyer , Stamatis Vassiliadis , Bartholomew Blaner
IPC分类号： G06F15/00 , G06F9/00 , G06F9/38 , G06F13/38 , G06F9/40
CPC分类号： G06F9/382 , G06F9/3853 , G06F9/3885
摘要： A digital computer system capable of processing two or more computer instructions in parallel and having a main memory unit for storing information blocks including the computer instructions includes an instruction compounding unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with another neighboring instruction. Tagged instructions are stored in the main memory. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to the functional units are obtained from the memory by way of a cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
摘要翻译：一种数字计算机系统，其能够并行处理两个或更多个计算机指令，并且具有用于存储包括计算机指令的信息块的主存储单元，包括用于分析指令的指令复合单元，并向每个指令添加指示是否指示的指示字段该指令可以与另一个相邻指令并行处理。标记的指令存储在主存储器中。计算机系统还包括彼此并行操作的多个功能指令处理单元。提供给功能单元的指令通过高速缓存存储单元从存储器获得。在指令发布时，根据其操作代码字段的编码，检查指令的标签字段并将用于并行处理的标记字段发送到不同的功能单元。

9. 发明申请

US20080256347A1 METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PATH-CORRELATED INDIRECT ADDRESS PREDICTIONS 有权
标题翻译：用于路径相关的间接地址预测的方法，系统和计算机程序产品
公开(公告)号：US20080256347A1
公开(公告)日：2008-10-16
申请号：US11734519
申请日：2007-04-12
申请人： Richard J. Eickemeyer , Michael K. Gschwind , Ravi Nair , Robert A. Philhower
发明人： Richard J. Eickemeyer , Michael K. Gschwind , Ravi Nair , Robert A. Philhower
IPC分类号： G06F9/30
CPC分类号： G06F9/3848
摘要： A method, system, and computer program product are provided, for maintaining a path history register of register indirect branches. A set of bits is generated based on a set of target address bits using a hit selection and/or a hash function operation, and the generated set of bits is inserted into a path history register by shifting bits in the path history register and/or applying a hash operation, information corresponding to prior history is removed from the path history register, using a shift out operation and/or a hash operation. The path, history register is used to maintain a recent target, table and generate register-indirect branch target address predictions based on path history correlation between register-indirect branches captured by the path history register.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于维护寄存器间接分支的路径历史寄存器。使用命中选择和/或散列函数操作，基于一组目标地址位产生一组位，并且通过将路径历史寄存器中的位移位和/或将该生成的位组插入到路径历史寄存器中使用散列操作，使用移出操作和/或散列操作从路径历史寄存器中移除与先前历史相对应的信息。路径历史寄存器用于维护最近的目标，表格，并根据由路径历史寄存器捕获的寄存器间接分支之间的路径历史相关性生成寄存器间接分支目标地址预测。

10. 发明授权

US5355460A In-memory preprocessor for compounding a sequence of instructions for parallel computer system execution 失效
标题翻译：内存预处理器，用于复合并行计算机系统执行指令序列
公开(公告)号：US5355460A
公开(公告)日：1994-10-11
申请号：US98240
申请日：1993-07-29
申请人： Richard J. Eickemeyer , Stamatis Vassiliadis , Bartholomew Blaner
发明人： Richard J. Eickemeyer , Stamatis Vassiliadis , Bartholomew Blaner
IPC分类号： G06F15/00 , G06F9/00 , G06F9/38 , G06F13/38 , G06F9/40
CPC分类号： G06F9/382 , G06F9/3853 , G06F9/3885
摘要： A digital computer system capable of processing two or more computer instructions in parallel and having a main memory unit for storing information blocks including the computer instructions includes an instruction compounding unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with another neighboring instruction. Tagged instructions are stored in the main memory. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to the functional units are obtained from the memory by way of a cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
摘要翻译：一种数字计算机系统，其能够并行处理两个或更多个计算机指令，并且具有用于存储包括计算机指令的信息块的主存储单元，包括用于分析指令的指令复合单元，并向每个指令添加指示是否指示的指示字段该指令可以与另一个相邻指令并行处理。标记的指令存储在主存储器中。计算机系统还包括彼此并行操作的多个功能指令处理单元。提供给功能单元的指令通过高速缓存存储单元从存储器获得。在指令发布时，根据其操作代码字段的编码，检查指令的标签字段并将用于并行处理的标记字段发送到不同的功能单元。

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