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1. 发明申请

US20090055153A1 Augmenting of Automated Clustering-Based Trace Sampling Methods by User-Directed Phase Detection 有权
标题翻译：通过用户定向相位检测来增强基于自动聚类的跟踪采样方法
公开(公告)号：US20090055153A1
公开(公告)日：2009-02-26
申请号：US11842337
申请日：2007-08-21
申请人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen , Pattabi R. Seshadri , John-David Wellman
发明人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen , Pattabi R. Seshadri , John-David Wellman
IPC分类号： G06F9/455
CPC分类号： G06F9/455 , G06F11/3636 , G06F11/3664
摘要： Computer implemented method, system, and computer usable program code for simulating processor operation in a data processing system. An instruction trace is generated, wherein the instruction trace includes markers specified by a user for identifying interval boundaries for at least one interval of the instruction trace. The instruction trace is divided into a plurality of intervals in consideration of the markers, and the plurality of intervals are formed into a plurality of interval clusters, wherein each interval cluster represents one phase of execution of the instruction trace. At least one interval from each of the plurality of interval clusters is selected as a trace sample to provide a plurality of trace samples, wherein each selected interval is of at least a minimum size, a simulation is performed using the plurality of trace samples, and a result of the simulation is provided to the user.
摘要翻译：用于在数据处理系统中模拟处理器操作的计算机实现的方法，系统和计算机可用程序代码。生成指令轨迹，其中指令轨迹包括由用户指定的用于识别指令轨迹的至少一个间隔的间隔边界的标记。考虑到标记，指令轨迹被分成多个间隔，并且多个间隔被形成为多个间隔簇，其中每个间隔簇表示指令轨迹的执行的一个阶段。选择来自多个间隔群集中的每一个的至少一个间隔作为跟踪样本以提供多个跟踪样本，其中每个选择的间隔至少为最小尺寸，使用多个迹线样本进行模拟，以及向用户提供模拟的结果。

2. 发明申请

US20090276191A1 Method And Apparatus For Integrated Circuit Design Model Performance Evaluation Using Basic Block Vector Clustering And Fly-By Vector Clustering 有权
标题翻译：使用基本块矢量聚类和飞行矢量聚类的集成电路设计模型性能评估的方法和装置
公开(公告)号：US20090276191A1
公开(公告)日：2009-11-05
申请号：US12112035
申请日：2008-04-30
申请人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
发明人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/318357 , G06F11/3428 , G06F11/3457 , G06F11/3664
摘要： A test system or simulator includes an enhanced IC test application sampling software program that executes test application software on a semiconductor die IC design model. The enhanced test application sampling software may include trace, simulation point, CPI error, clustering, instruction budgeting, and other programs. The enhanced test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software workloads. The enhanced test application sampling software utilizes the microarchitecture dependent information to generate the FBVs to select representative instruction intervals from the test application software. The enhanced test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing a global instruction budgeting analysis method. Designers use the test system with enhanced test application sampling software to evaluate IC design models by using the representative test application software program.
摘要翻译：测试系统或模拟器包括在半导体芯片IC设计模型上执行测试应用软件的增强型IC测试应用采样软件程序。增强的测试应用程序采样软件可能包括跟踪，模拟点，CPI错误，聚类，指令预算和其他程序。增强的测试应用采样软件从测试应用软件工作负载的指令跟踪分析中生成基本块向量（BBV）和飞越向量（FBV）。增强的测试应用采样软件利用微架构依赖信息生成FBV，以从测试应用软件中选择代表性指令间隔。增强的测试应用采样软件利用全球指令预算分析方法，从BBV和FBV数据生成代表性测试应用软件程序。设计人员使用带有增强型测试应用程序采样软件的测试系统，通过使用代表性的测试应用软件程序来评估IC设计模型。

3. 发明申请

US20110320793A1 OPERATING SYSTEM AWARE BRANCH PREDICTOR USING A DYNAMICALLY RECONFIGURABLE BRANCH HISTORY TABLE 有权
标题翻译：使用动态可重新分支历史表的操作系统AWARE分支预测器
公开(公告)号：US20110320793A1
公开(公告)日：2011-12-29
申请号：US12823288
申请日：2010-06-25
申请人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen
发明人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen
IPC分类号： G06F9/38
CPC分类号： G06F9/5011 , G06F9/3848 , G06F2209/507
摘要： A processor resource manager assigns a branch history resource to a first execution mode. The branch history resource is utilized for predicting a branch direction of a branch instruction. Next, the resource manager logs a number of branch mispredictions that occur while the processor executes a second execution mode. The resource manager, in turn, reassigns the branch history resource to the second execution mode based upon the number of branch mispredictions.
摘要翻译：处理器资源管理器将分支历史资源分配给第一执行模式。分支历史资源用于预测分支指令的分支方向。接下来，资源管理器记录在处理器执行第二执行模式时发生的多个分支错误预测。资源管理器又根据分支错误预测的数量将分支历史资源重新分配到第二执行模式。

4. 发明申请

US20090182994A1 TWO-LEVEL REPRESENTATIVE WORKLOAD PHASE DETECTION METHOD, APPARATUS, AND COMPUTER USABLE PROGRAM CODE 有权
标题翻译：两级代表性工作负载相位检测方法，装置和计算机可用程序代码
公开(公告)号：US20090182994A1
公开(公告)日：2009-07-16
申请号：US11972678
申请日：2008-01-11
申请人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Pattabi Michael Seshadri , Madhavi Gopal Valluri
发明人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Pattabi Michael Seshadri , Madhavi Gopal Valluri
IPC分类号： G06F9/30
CPC分类号： G06F11/3414 , G06F11/3476 , G06F2201/885
摘要： A method, apparatus, and computer-usable program code in a computer system for identifying a subset of a workload, which includes a total set of dynamic instructions, to use as a trace. Processor unit hardware executes the entire workload in real-time using a particular dataset. The processor unit hardware includes at least one microprocessor and at least one cache. The real-time execution of the workload is monitored to obtain information about how the processor unit hardware executes the workload when the workload is executed using the particular dataset to form actual performance information. Multiple different subsets of the workload are generated. The execution of each one of the subsets by the processor unit hardware is compared with the actual performance information. A result of the comparison is used to select one of the plurality of different subsets that roost closely represents the execution of the entire workload using the particular dataset to use as a trace.
摘要翻译：一种计算机系统中的方法，装置和计算机可用的程序代码，用于识别工作负载的子集，其包括一组动态指令，用作跟踪。处理器单元硬件使用特定数据集实时执行整个工作负载。处理器单元硬件包括至少一个微处理器和至少一个高速缓存。监视工作负载的实时执行，以获取有关当使用特定数据集执行工作负载以形成实际性能信息时处理器单元硬件如何执行工作负载的信息。生成多个不同的工作负载子集。将处理器单元硬件的每个子集的执行与实际的性能信息进行比较。比较的结果被用于选择多个不同的子集中的一个，这些子集中使用特定的数据集作为跟踪来密切地表示整个工作负荷的执行。

5. 发明申请

US20130111135A1 VARIABLE CACHE LINE SIZE MANAGEMENT 有权
标题翻译：可变缓存线尺寸管理
公开(公告)号：US20130111135A1
公开(公告)日：2013-05-02
申请号：US13286507
申请日：2011-11-01
申请人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F12/0811 , G06F12/0897
摘要： According to one aspect of the present disclosure, a system and technique for variable cache line size management is disclosed. The system includes a processor and a cache hierarchy, where the cache hierarchy includes a sectored upper level cache and an unsectored lower level cache, and wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache. The system also includes logic executable to, responsive to determining that a cache line from the upper level cache is to be evicted to the lower level cache: identify referenced sub-sectors of the cache line to be evicted; invalidate unreferenced sub-sectors of the cache line to be evicted; and store the referenced sub-sectors in the lower level cache.
摘要翻译：根据本公开的一个方面，公开了一种用于可变高速缓存行大小管理的系统和技术。该系统包括处理器和高速缓存层级，其中高速缓存分层结构包括扇区高级缓存和未被覆盖的较低级高速缓存，并且其中高级高速缓存包括多个子扇区，每个子扇区具有高速缓存行大小对应于较低级别缓存的高速缓存行大小。该系统还包括可执行的逻辑，用于响应于确定来自较高级别高速缓存的高速缓存线将被驱逐到较低级高速缓存：识别要驱逐的高速缓存行的参考子扇区; 使缓存行的未引用子扇区无效; 并将参考的子扇区存储在较低级别的高速缓存中。

6. 发明申请

US20090186494A1 APPARATUS, SYSTEM, AND METHOD FOR A CONFIGURABLE BLADE CARD 有权
标题翻译：用于可配置刀片的设备，系统和方法
公开(公告)号：US20090186494A1
公开(公告)日：2009-07-23
申请号：US12016043
申请日：2008-01-17
申请人： Robert H. Bell, JR. , Jose R. Escalera , Octavian F. Herescu , Vernon W. Miller , Michael D. Roll
发明人： Robert H. Bell, JR. , Jose R. Escalera , Octavian F. Herescu , Vernon W. Miller , Michael D. Roll
IPC分类号： H01R12/00
CPC分类号： G06F13/409 , H05K7/1487
摘要： An apparatus, system, and method are disclosed for a configurable blade card. A base card is in physical and electrical communication with a blade connector. The blade connector is in physical and electrical communication with a blade enclosure connector. A secondary card is in physical and electrical communication with the base card to form a blade card. A coupler physically couples the base card and the secondary card. The base card and the secondary card are co-planar and compatible with a blade card form factor.
摘要翻译：公开了一种用于可配置的刀片卡的装置，系统和方法。基卡与刀片连接器物理和电气通信。刀片连接器与刀片机箱连接器物理和电气通信。辅助卡与基卡进行物理和电气通信以形成刀片卡。耦合器物理耦合基卡和辅助卡。基卡和辅助卡是共面的，与刀片卡形状兼容。

7. 发明申请

US20090138220A1 Power-aware line intervention for a multiprocessor directory-based coherency protocol 审中-公开
标题翻译：基于多处理器目录的一致性协议的功率感知线路干预
公开(公告)号：US20090138220A1
公开(公告)日：2009-05-28
申请号：US11946551
申请日：2007-11-28
申请人： Robert H. Bell, JR. , Louis B. Capps, JR. , Thomas E. Cook , Michael J. Shapiro , Naresh Nayar
发明人： Robert H. Bell, JR. , Louis B. Capps, JR. , Thomas E. Cook , Michael J. Shapiro , Naresh Nayar
IPC分类号： G01R21/02 , G06F12/08
CPC分类号： G06F12/0817 , Y02D10/13
摘要： A directory-based coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e.g., at cores, cache memories, memory controller, etc.) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.
摘要翻译：基于目录的一致性方法，系统和程序被提供用于基于每个存储器源处的感测温度或功率耗散值来在多处理器系统中从多个候选存储器源插入所请求的高速缓存行。通过在共享所请求的高速缓存行的每个候选存储器源（例如，在内核，高速缓冲存储器，存储器控制器等）中提供温度或功率耗散传感器，可以使用控制逻辑来确定哪个存储器源应该来源于高速缓存通过使用功率传感器信号仅以可接受的功率消耗信号通知存储器源，以向请求器提供高速缓存线。

8. 发明申请

US20130145135A1 PERFORMANCE OF PROCESSORS IS IMPROVED BY LIMITING NUMBER OF BRANCH PREDICTION LEVELS 有权
标题翻译：通过限制分支预测水平数来改进处理器的性能
公开(公告)号：US20130145135A1
公开(公告)日：2013-06-06
申请号：US13308696
申请日：2011-12-01
申请人： Robert H. Bell, JR. , Wen-Tzer T. Chen
发明人： Robert H. Bell, JR. , Wen-Tzer T. Chen
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3844 , G06F9/3842 , G06F11/30 , G06F11/3024 , G06F11/3409 , G06F2201/81
摘要： A method utilizes information provided by performance monitoring hardware to dynamically adjust the number of levels of speculative branch predictions allowed (typically 3 or 4 per thread). for a processor core. The information includes cycles-per-instruction (CPI) for the processor core and number of memory accesses per unit time. If the CPI is below a CPI threshold; and the number of memory accesses (NMA) per unit time is above a prescribe threshold, the number of levels of speculative branch predictions is reduced per thread for the processor core. Likewise, the number of levels of speculative branch predictions could be increased, from a low level to maximum allowed, if the CPI threshold is exceeded or the number of memory accesses per unit time is below the prescribed threshold.
摘要翻译：一种方法利用由性能监视硬件提供的信息来动态地调整允许的推测分支预测级别的数量（通常每线程3或4个）。用于处理器核心。该信息包括处理器核心的每个指令周期（CPI）和每单位时间的存储器访问次数。如果CPI低于CPI阈值; 并且每单位时间的存储器访问次数（NMA）高于规定阈值，则针对处理器核的每个线程的推测分支预测的级别数量减少。同样地，如果超过CPI阈值或每单位时间的存储器访问次数低于规定的阈值，则可以将推测分支预测的级数从低级别增加到允许的最大级别。

9. 发明申请

US20120130928A1 EFFICIENT STORAGE OF INDIVIDUALS FOR OPTIMIZATION SIMULATION 有权
标题翻译：有效存储个人优化模拟
公开(公告)号：US20120130928A1
公开(公告)日：2012-05-24
申请号：US12948850
申请日：2010-11-18
申请人： Robert H. Bell, JR. , Jason F. Cantin
发明人： Robert H. Bell, JR. , Jason F. Cantin
IPC分类号： G06N3/12 , G06F15/18
CPC分类号： G06N3/126
摘要： Candidate solutions to an optimization problem comprise a set of potential values that can be applied to variables in a problem description. Candidate solutions can be large because of the complexity of optimization problems and large number of variables. The populations of candidate solutions may also be large to ensure diversity and effectiveness in computing a solution. When the populations and the candidate solutions are large for an optimization problem, computing a solution to the optimization problem consumes a large amount of memory. In some instances, several generations of candidate solutions are stored in memory. Compression of the candidate solutions can minimize the memory space consumed to compute a solution to an optimization problem.
摘要翻译：优化问题的候选解决方案包括可以应用于问题描述中的变量的一组潜在值。候选解决方案可能很大，因为优化问题和大量变量的复杂性。候选解决方案的人数也可能很大，以确保计算解决方案的多样性和有效性。当人口和候选解决方案对于优化问题很大时，计算优化问题的解决方案会消耗大量的内存。在某些情况下，几代候选解决方案存储在内存中。压缩候选解决方案可以最大限度地减少计算优化问题解决方案所消耗的内存空间。

10. 发明申请

US20120096240A1 Application Performance with Support for Re-Initiating Unconfirmed Software-Initiated Threads in Hardware 有权
公开(公告)号：US20120096240A1
公开(公告)日：2012-04-19
申请号：US12905176
申请日：2010-10-15
申请人： Matthew Accapadi , Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Matthew Accapadi , Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/38 , G06F9/455 , G06F9/30
CPC分类号： G06F9/505 , G06F12/0862 , G06F2209/503 , G06F2212/6026
摘要： A method, system and computer-usable medium are disclosed for managing prefetch streams in a virtual machine environment. Compiled application code in a first core, which comprises a Special Purpose Register (SPR) and a plurality of first prefetch engines, initiates a prefetch stream request. If the prefetch stream request cannot be initiated due to unavailability of a first prefetch engine, then an indicator bit indicating a Prefetch Stream Dispatch Fault is set in the SPR, causing a Hypervisor to interrupt the execution of the prefetch stream request. The Hypervisor then calls its associated operating system (OS), which determines prefetch engine availability for a second core comprising a plurality of second prefetch engines. If a second prefetch engine is available, then the OS migrates the prefetch stream request from the first core to the second core, where it is initiated on an available second prefetch engine.

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