专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120002812A1 DATA AND CONTROL ENCRYPTION 有权
标题翻译：数据和控制加密
公开(公告)号：US20120002812A1
公开(公告)日：2012-01-05
申请号：US12828080
申请日：2010-06-30
申请人： Robert H. Bell, JR. , Louis B. Capps, JR. , Michael J. Shapiro
发明人： Robert H. Bell, JR. , Louis B. Capps, JR. , Michael J. Shapiro
IPC分类号： H04L9/20 , H04L9/08 , H04K1/04 , H04L9/18
CPC分类号： H04L9/06 , H04L9/0618 , H04L2209/125
摘要： Secure communication of data between devices includes encrypting unencrypted data at a first device by reordering unencrypted bits provided in parallel on a device bus, including data and control bits, from an unencrypted order to form encrypted data including a plurality of encrypted bits in parallel in an encrypted order defined by a key. The encrypted data may be transmitted to another device where the encrypted data is decrypted by using the key to order the encrypted bits to restore the unencrypted order thereby to reform the unencrypted data.
摘要翻译：设备之间的数据的安全通信包括通过从未加密的顺序重新排序设备总线（包括数据和控制位）并行提供的未加密比特来在第一设备处对未加密的数据进行加密，以形成包括多个加密比特的加密数据由密钥定义的加密顺序。加密数据可以通过使用密钥来对加密数据进行解密的另一设备发送到另一个设备，以对加密的比特进行命令以恢复未加密的顺序，从而改变未加密的数据。

2. 发明申请

US20090164812A1 Dynamic processor reconfiguration for low power without reducing performance based on workload execution characteristics 失效
标题翻译：动态处理器重新配置为低功耗，而不会降低基于工作负载执行特性的性能
公开(公告)号：US20090164812A1
公开(公告)日：2009-06-25
申请号：US11960163
申请日：2007-12-19
申请人： Louis B. Capps, JR. , Robert H. Bell, JR. , Michael J. Shapiro
发明人： Louis B. Capps, JR. , Robert H. Bell, JR. , Michael J. Shapiro
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3243 , Y02D10/152 , Y02D50/20
摘要： A method, system and program are provided for dynamically reconfiguring a pipelined processor to operate with reduced power consumption without reducing existing performance. By monitoring or detecting the performance of individual units or stages in the processor as they execute a given workload, each stage may use high-performance circuitry until such time as a drop in the throughput performance is detected, at which point the stages are reconfigured to use lower-performance circuitry so as to meet the reduced performance throughput requirements using less power. By configuring the processor to back off from high-performance designs to low-performance designs to meet the detected performance characteristics of the executing workload warrant, power dissipation may be optimized.
摘要翻译：提供了一种方法，系统和程序，用于动态重新配置流水线处理器，以降低功耗进行操作，而不会降低现有性能。通过在处理器执行给定工作负载时监视或检测处理器中的各个单元或级的性能，每个级可以使用高性能电路，直到检测到吞吐量性能下降为止，此时将级重新配置为使用低性能电路，以便通过更少的功率来满足降低的性能吞吐量要求。通过将处理器配置为从高性能设计退回到低性能设计，以满足检测到的执行工作量保证的性能特征，可以优化功耗。

3. 发明申请

US20090138660A1 Power-aware line intervention for a multiprocessor snoop coherency protocol 有权
标题翻译：多处理器侦听一致性协议的功率感知线路干预
公开(公告)号：US20090138660A1
公开(公告)日：2009-05-28
申请号：US11946249
申请日：2007-11-28
申请人： Robert H. Bell, JR. , Louis B. Capps, JR. , Thomas E. Cook , Michael J. Shapiro , Naresh Nayar
发明人： Robert H. Bell, JR. , Louis B. Capps, JR. , Thomas E. Cook , Michael J. Shapiro , Naresh Nayar
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F2212/1028 , Y02D10/13
摘要： A snoop coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e.g., at cores, cache memories, memory controller, etc.) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.
摘要翻译：提供窥探一致性方法，系统和程序，用于基于每个存储器源处的感测温度或功率耗散值，在多处理器系统中从多个候选存储器源插入所请求的高速缓存行。通过在共享所请求的高速缓存行的每个候选存储器源（例如，在内核，高速缓冲存储器，存储器控制器等）中提供温度或功率耗散传感器，可以使用控制逻辑来确定哪个存储器源应该来源于高速缓存通过使用功率传感器信号仅以可接受的功率消耗信号通知存储器源，以向请求器提供高速缓存线。

4. 发明授权

US07962770B2 Dynamic processor reconfiguration for low power without reducing performance based on workload execution characteristics 失效
标题翻译：动态处理器重新配置为低功耗，而不会降低基于工作负载执行特性的性能
公开(公告)号：US07962770B2
公开(公告)日：2011-06-14
申请号：US11960163
申请日：2007-12-19
申请人： Louis B. Capps, Jr. , Robert H. Bell, Jr. , Michael J. Shapiro
发明人： Louis B. Capps, Jr. , Robert H. Bell, Jr. , Michael J. Shapiro
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3243 , Y02D10/152 , Y02D50/20
摘要： A method, system and program are provided for dynamically reconfiguring a pipelined processor to operate with reduced power consumption without reducing existing performance. By monitoring or detecting the performance of individual units or stages in the processor as they execute a given workload, each stage may use high-performance circuitry until such time as a drop in the throughput performance is detected, at which point the stages are reconfigured to use lower-performance circuitry so as to meet the reduced performance throughput requirements using less power. By configuring the processor to back off from high-performance designs to low-performance designs to meet the detected performance characteristics of the executing workload warrant, power dissipation may be optimized.
摘要翻译：提供了一种方法，系统和程序，用于动态重新配置流水线处理器，以降低功耗进行操作，而不会降低现有性能。通过在处理器执行给定工作负载时监视或检测处理器中的各个单元或级的性能，每个级可以使用高性能电路，直到检测到吞吐量性能下降为止，此时将级重新配置为使用低性能电路，以便通过更少的功率来满足降低的性能吞吐量要求。通过将处理器配置为从高性能设计退回到低性能设计，以满足检测到的执行工作量保证的性能特征，可以优化功耗。

5. 发明申请

US20100153956A1 Multicore Processor And Method Of Use That Configures Core Functions Based On Executing Instructions 有权
标题翻译：基于执行指令配置核心功能的多核处理器和使用方法
公开(公告)号：US20100153956A1
公开(公告)日：2010-06-17
申请号：US12335696
申请日：2008-12-16
申请人： Louis B. Capps, JR. , Ronald E. Newhart , Thomas E. Cook , Robert H. Bell, JR. , Michael J. Shapiro
发明人： Louis B. Capps, JR. , Ronald E. Newhart , Thomas E. Cook , Robert H. Bell, JR. , Michael J. Shapiro
IPC分类号： G06F9/46 , G06F9/30
CPC分类号： G06F9/30145 , G06F9/30021 , G06F9/3802 , G06F9/5044 , G06F11/3024 , G06F11/3409 , G06F15/80 , G06F2209/501
摘要： A multiprocessor system having plural heterogeneous processing units schedules instruction sets for execution on a selected of the processing units by matching workload processing characteristics of processing units and the instruction sets. To establish an instruction set's processing characteristics, the homogeneous instruction set is executed on each of the plural processing units with one or more performance metrics tracked at each of the processing units to determine which processing unit most efficiently executes the instruction set. Instruction set workload processing characteristics are stored for reference in scheduling subsequent execution of the instruction set.
摘要翻译：具有多个异构处理单元的多处理器系统通过匹配处理单元的工作负载处理特性和指令集来调度在所选择的处理单元上执行的指令集。为了建立指令集的处理特性，通过在每个处理单元跟踪的一个或多个性能度量在多个处理单元中的每一个上执行均匀指令集，以确定哪个处理单元最有效地执行指令集。指令集工作负载处理特性被存储以用于调度指令集的后续执行。

6. 发明申请

US20090138682A1 Dynamic instruction execution based on transaction priority tagging 有权
标题翻译：基于事务优先级标记的动态指令执行
公开(公告)号：US20090138682A1
公开(公告)日：2009-05-28
申请号：US11946504
申请日：2007-11-28
申请人： Louis B. Capps, JR. , Robert H. Bell, JR.
发明人： Louis B. Capps, JR. , Robert H. Bell, JR.
IPC分类号： G06F9/30
CPC分类号： G06F9/30101 , G06F9/3851 , G06F9/5011 , G06F11/3409 , G06F11/3466 , G06F2201/81 , G06F2201/885 , G06F2209/507 , Y02D10/22 , Y02D10/34
摘要： A method, system and program are provided for dynamically assigning priority values to instruction threads in a computer system based on one or more predetermined thread performance tests, and using the assigned instruction priorities to determine how resources are used in the system. By storing the assigning priority values for each thread as a tag in the thread's instructions, tagged instructions from different threads that are dispatched through the system are allocated system resources based on the tagged priority values assigned to the respective instruction threads. Priority values for individual threads may be updated with control software which tests thread performance and uses the test results to apply predetermined adjustment policies. The test results may be used to optimize the workload allocation of system resources by dynamically assigning thread priority values to individual threads using any desired policy, such as achieving thread execution balance relative to thresholds and to performance of other threads, reducing thread response time, lowering power consumption, etc.
摘要翻译：提供了一种方法，系统和程序，用于基于一个或多个预定的线程性能测试来动态地为计算机系统中的指令线程分配优先级值，并且使用所分配的指令优先级来确定如何在系统中使用资源。通过将每个线程的分配优先级值作为标签存储在线程的指令中，基于分配给各个指令线程的标记的优先级值来分配来自系统调度的来自不同线程的标记指令。可以使用测试线程性能的控制软件更新各个线程的优先级值，并使用测试结果来应用预定的调整策略。测试结果可用于通过使用任何期望的策略动态地将线程优先级值分配给各个线程来优化系统资源的工作量分配，例如实现相对于阈值的线程执行平衡以及其他线程的性能，减少线程响应时间，降低功耗等

7. 发明授权

US5430860A Mechanism for efficiently releasing memory lock, after allowing completion of current atomic sequence 失效
标题翻译：允许完成当前原子序列后有效释放内存锁的机制
公开(公告)号：US5430860A
公开(公告)日：1995-07-04
申请号：US761095
申请日：1991-09-17
申请人： Louis B. Capps, Jr. , Philip E. Milling , Warren E. Price
发明人： Louis B. Capps, Jr. , Philip E. Milling , Warren E. Price
IPC分类号： G06F13/14 , G06F13/00
CPC分类号： G06F13/14
摘要： A logic circuit mechanism for inducing a processing unit to release a LOCK signal that the processing unit uses to secure continuous access to a memory system during read modify write operations requiring "atomic" (continuous) access. The processing unit has an internal cache enabling it to set up consecutive memory access operations at a pace such that the LOCK signal could be held continuously active while a string of atomic memory accesses is carried out. The present circuit mechanism prevents premature release of the processing unit's LOCK signal, by asserting a Hold signal which requires the processing unit to release its LOCK signal but only after that unit has fully completed its current atomic access operation. The logic circuit reduces its impact on processing unit performance by detecting when the LOCK signal has been active continuously for N consecutive atomic operations coinciding with external contention, and calling for release of the CPUs LOCK signal only while the Nth such operation is being conducted.
摘要翻译：一种逻辑电路机构，用于在读取需要“原子”（连续）访问的修改写入操作期间，引导处理单元释放处理单元用于确保对存储器系统的连续访问的LOCK信号。处理单元具有内部高速缓存，使得其能够以一定的速度建立连续的存储器访问操作，使得当执行一串原子存储器访问时，LOCK信号可以被持续地活动。本电路机制通过断言需要处理单元释放其LOCK信号但仅在该单元完全完成其当前的原子访问操作之后的保持信号来防止处理单元的LOCK信号的过早释放。逻辑电路通过检测LOCK信号何时连续激活N次连续的原子操作，与外部争用一致，从而降低对处理单元性能的影响，并且仅在执行第N次操作时才要求释放CPU LOCK信号。

8. 发明授权

US07870337B2 Power-aware line intervention for a multiprocessor snoop coherency protocol 有权
标题翻译：多处理器侦听一致性协议的功率感知线路干预
公开(公告)号：US07870337B2
公开(公告)日：2011-01-11
申请号：US11946249
申请日：2007-11-28
申请人： Robert H. Bell, Jr. , Louis B. Capps, Jr. , Thomas E. Cook , Michael J. Shapiro , Naresh Nayar
发明人： Robert H. Bell, Jr. , Louis B. Capps, Jr. , Thomas E. Cook , Michael J. Shapiro , Naresh Nayar
IPC分类号： G06F13/00 , G06F13/28 , G01R21/00 , G01R21/06 , G01R19/00
CPC分类号： G06F12/0831 , G06F2212/1028 , Y02D10/13
摘要： A snoop coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e.g., at cores, cache memories, memory controller, etc.) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.
摘要翻译：提供窥探一致性方法，系统和程序，用于基于每个存储器源处的感测温度或功率耗散值，在多处理器系统中从多个候选存储器源插入所请求的高速缓存行。通过在共享所请求的高速缓存行的每个候选存储器源（例如，在内核，高速缓冲存储器，存储器控制器等）中提供温度或功率耗散传感器，可以使用控制逻辑来确定哪个存储器源应该来源于高速缓存通过使用功率传感器信号仅以可接受的功率消耗信号通知存储器源，以向请求器提供高速缓存线。

9. 发明授权

US07420378B2 Power grid structure to optimize performance of a multiple core processor 失效
标题翻译：电网结构优化多核处理器的性能
公开(公告)号：US07420378B2
公开(公告)日：2008-09-02
申请号：US11456658
申请日：2006-07-11
申请人： Jean Audet , Louis B. Capps, Jr. , Glenn G. Daves , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
发明人： Jean Audet , Louis B. Capps, Jr. , Glenn G. Daves , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
IPC分类号： G01R31/08 , G06F19/00
CPC分类号： G06F1/3203 , G06F1/26 , G06F1/3296 , H01L23/50 , H01L2924/0002 , Y02D10/172 , H01L2924/00
摘要： A reduced number of voltage regulator modules provides a reduced number of supply voltages to the package. The package includes a voltage plane for each of the voltage regulator modules. Each core or other component on the die is tied to a switch on the package, and each switch is electrically connected to all of the voltage planes. A wafer-level test determines a voltage that optimizes performance of each core or other component. Given these voltage values, an engineer may determine voltage settings for the voltage regulator modules and which cores are to be connected to which voltage regulator modules. A database stores voltage setting data, such as the optimal voltage for each component, switch values, or voltage settings for each voltage regulator module. An engineering wire may permanently set each switch to customize the voltage supply to each core or other component.
摘要翻译：减少数量的电压调节器模块为封装提供了减少的电源电压数量。该封装包括用于每个电压调节器模块的电压平面。管芯上的每个核心或其他部件连接到封装上的开关，并且每个开关电连接到所有电压平面。晶圆级测试确定优化每个核心或其他组件的性能的电压。给定这些电压值，工程师可以确定电压调节器模块的电压设置以及要连接到哪些电压调节器模块的哪些核心。数据库存储电压设置数据，例如每个组件的最佳电压，开关值或每个电压调节器模块的电压设置。工程线可以永久地设置每个开关以定制每个芯或其他部件的电压供应。

10. 发明授权

US07268570B1 Apparatus and method for customized burn-in of cores on a multicore microprocessor integrated circuit chip 失效
标题翻译：在多核微处理器集成电路芯片上定制化核心的装置和方法
公开(公告)号：US07268570B1
公开(公告)日：2007-09-11
申请号：US11426646
申请日：2006-06-27
申请人： Jean Audet , Louis B. Capps, Jr. , Glenn G. Daves , Joanne Ferris , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
发明人： Jean Audet , Louis B. Capps, Jr. , Glenn G. Daves , Joanne Ferris , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
IPC分类号： G01R31/02
CPC分类号： G01R31/2855
摘要： An apparatus and method for providing a multi-core integrated circuit chip that reduces the cost of the package and board while optimizing performance of the cores for use with a single voltage plane. The apparatus and method of the illustrative embodiments make use of a dynamic burn-in technique that optimizes all of the cores on the chip to run at peak performance at a single voltage. Each core is burned-in with a customized burn-in voltage that provides uniform power and performance across the whole chip. This results in a higher burn-in yield and lower overall power in the integrated circuit chip. The optimization of the cores to run at peak performance at a single voltage is achieved through use of the negative bias temperature instability affects on the cores imparted by the burn-in voltages applied.
摘要翻译：一种用于提供多核集成电路芯片的装置和方法，其降低了封装和板的成本，同时优化用于单个电压平面的芯的性能。说明性实施例的装置和方法使用动态老化技术，其优化芯片上的所有核心以在单个电压下以峰值性能运行。每个核心都具有定制的老化电压，可在整个芯片上提供均匀的功率和性能。这导致集成电路芯片中更高的老化成本和更低的总功率。通过使用负偏置温度不稳定性影响由所施加的老化电压施加的磁芯，可以实现在单电压下以峰值性能运行的磁芯的优化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式