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1. 发明申请

US20060200726A1 Failure trend detection and correction in a data storage array 审中-公开
标题翻译：数据存储阵列中的故障趋势检测和校正
公开(公告)号：US20060200726A1
公开(公告)日：2006-09-07
申请号：US11070942
申请日：2005-03-03
申请人： Robert Gittins , Robert Lester
发明人： Robert Gittins , Robert Lester
IPC分类号： G11C29/00
CPC分类号： G06F11/0751 , G06F11/0727 , G06F11/0793 , G11B27/36 , G11B2220/2516 , G11B2220/41
摘要： Method and apparatus for detecting and correcting parametric failure trends in a data storage array. A plurality of data storage devices, such as hard disc drives, are arranged to form a multi-device addressable memory array space. A controller controls access to the array space, and is configured to accumulate operational performance data from each of the devices into a history log. A statistical analysis engine of the controller analyzes the data to detect anomalous operation of the devices, including a horizontal analysis of data across multiple devices. The controller initiates a data storage device specific corrective action event in response to the analysis, as required. The analysis by the engine can be in addition to, or in lieu of, analysis by the individual devices. A data request block requests additional data samples for a given parameter, or requests additional parametric data to further the analysis.
摘要翻译：用于检测和校正数据存储阵列中的参数故障趋势的方法和装置。多个数据存储设备（诸如硬盘驱动器）被布置成形成多设备可寻址存储器阵列空间。控制器控制对阵列空间的访问，并且被配置为将来自每个设备的操作性能数据累积到历史记录日志中。控制器的统计分析引擎分析数据以检测设备的异常操作，包括横跨多个设备的数据分析。根据需要，控制器根据分析启动特定的数据存储设备的纠正措施事件。发动机的分析可以是各个装置的分析或替代分析。数据请求块向给定参数请求附加数据样本，或请求附加参数数据以进一步分析。

2. 发明申请

US20050027951A1 Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency 有权
标题翻译：支持非均匀内存多级条带化以最大化并发性的方法
公开(公告)号：US20050027951A1
公开(公告)日：2005-02-03
申请号：US10928046
申请日：2004-08-27
申请人： Gary Piccirillo , John MacLaren , Robert Lester , John Larson , Jerome Johnson , Benjamin Clark
发明人： Gary Piccirillo , John MacLaren , Robert Lester , John Larson , Jerome Johnson , Benjamin Clark
IPC分类号： G06F11/00 , G06F11/16 , G06F12/00
CPC分类号： G11C29/846 , G11C5/04 , G11C29/74 , G11C29/886 , G11C2029/0409 , G11C2029/0411
摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules.
摘要翻译：计算机系统包括包含半导体存储器（诸如DIMM）的多个存储器模块。该系统包括主机/数据控制器，其利用XOR引擎以条带方式在多个存储器模块上存储数据和奇偶校验信息，以创建工业标准DIMM（RAID）的冗余阵列。主机/数据控制器还交织与多个存储器模块中的每一个相关联的多个通道上的数据。

3. 发明申请

US20070266229A1 Encoding hardware end loop information onto an instruction 审中-公开
标题翻译：将硬件结束循环信息编码到指令上
公开(公告)号：US20070266229A1
公开(公告)日：2007-11-15
申请号：US11431732
申请日：2006-05-10
申请人： Erich Plondke , Robert Lester , Lucian Codrescu , Muhammad Ahmed
发明人： Erich Plondke , Robert Lester , Lucian Codrescu , Muhammad Ahmed
IPC分类号： G06F9/44
CPC分类号： G06F9/30149 , G06F9/325 , G06F9/3853 , G06F9/3885
摘要： Methods and apparatus for encoding information regarding a hardware loop of a set of packets is provided, each packet (400) containing instructions. The information is encoded into one or more bits of at least one instruction (300) in the set of packets. The information may indicate whether a packet is or is not an end packet of the loop. Information regarding two hardware loops may be encoded where information regarding the first loop is encoded into an instruction at a first position in each packet and information regarding the second loop is encoded into an instruction at a second position in each packet. End instruction information may be encoded into an instruction not having encoded loop information at the same bit positions reserved for the encoded loop information, the end instruction information indicating whether an instruction is the last instruction of a packet and the length of a packet.
摘要翻译：提供了用于编码关于一组分组的硬件循环的信息的方法和装置，每个分组（400）包含指令。信息被编码成该组分组中的至少一个指令（300）的一个或多个位。信息可以指示分组是否是循环的结束分组。关于两个硬件循环的信息可以被编码，其中关于第一循环的信息被编码为每个分组中的第一位置处的指令，并且关于第二循环的信息被编码为每个分组中的第二位置处的指令。结束指令信息可以被编码为在编码环路信息保留的相同位位置处不具有编码环路信息的指令，表示指令是分组的最后指令还是分组长度的结束指令信息。

4. 发明申请

US20060230259A1 Instruction memory unit and method of operation 有权
标题翻译：指令存储单元和操作方法
公开(公告)号：US20060230259A1
公开(公告)日：2006-10-12
申请号：US11104115
申请日：2005-04-11
申请人： Muhammad Ahmed , Lucian Codrescu , Erich Plondke , William Anderson , Robert Lester , Phillip Jones
发明人： Muhammad Ahmed , Lucian Codrescu , Erich Plondke , William Anderson , Robert Lester , Phillip Jones
IPC分类号： G06F9/00
CPC分类号： G06F9/325 , G06F9/3802 , G06F9/3804 , G06F9/381
摘要： An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of a forward program redirect construct, and issue a next program instruction already stored in the second memory structure if a resolution of the forward branching instruction is identical to a last resolution of the same. The second memory structure is further operable to issue a backward program redirect construct, determine whether a target instruction is stored in the second memory structure, issue the target instruction if the target instruction is stored in the second memory structure, and fetch the target instruction from the first memory structure if the target instruction is not stored in the second memory structure.
摘要翻译：指令存储单元包括可操作以存储程序指令的第一存储器结构，以及可操作以存储从第一存储器结构提取的程序指令并且发出用于执行的存储的程序指令的第二存储器结构。如果前向分支指令的分辨率与其最后一个分辨率相同，则第二存储器结构可操作以识别正向程序重定向构造的重复发出，并发出已经存储在第二存储器结构中的下一个程序指令。第二存储器结构还可操作以发出反向程序重定向结构，确定目标指令是否存储在第二存储器结构中，如果目标指令存储在第二存储器结构中，则发出目标指令，并从如果目标指令没有存储在第二存储器结构中的第一存储器结构。

5. 发明申请

US20060294118A1 Skip list with address related table structure 有权
标题翻译：跳过列表与地址相关的表结构
公开(公告)号：US20060294118A1
公开(公告)日：2006-12-28
申请号：US11166901
申请日：2005-06-24
申请人： Clark Lubbers , Robert Lester
发明人： Clark Lubbers , Robert Lester
IPC分类号： G06F7/00
CPC分类号： G06F12/0866 , G06F12/0864 , G06F17/30321 , G06F2212/311
摘要： Apparatus and method for efficiently arranging and searching data in a memory space, such as a cache memory of a data storage array controller. A data structure comprises a skip list of nodes having an array of forward pointers. Each node has a node level derived from an index at which the node is stored in a table in the memory space. The total available number of nodes is preferably selected to be less than half of the largest power of 2 that can be expressed by a number of bits of the index, and the nodes are preferably stored at only even or only odd indices of the table. In such case, a free list of nodes is preferably generated from an array of pairs of counts and indices to identify the available nodes. Additional table structures can further be provided to enhance data arrangement and searching functions.
摘要翻译：在诸如数据存储阵列控制器的高速缓冲存储器的存储器空间中有效地布置和搜索数据的装置和方法。数据结构包括具有前向指针阵列的节点的跳过列表。每个节点具有从节点存储在存储器空间中的表中的索引导出的节点级别。优选地，总可用数量的节点被选择为小于可以由索引的位数表示的2的最大功率的一半，并且节点优选地仅存储在表的偶数或只有奇数索引处。在这种情况下，优选地从计数和索引对的阵列生成节点的空闲列表以识别可用节点。可以进一步提供额外的表结构以增强数据排列和搜索功能。

6. 发明申请

US20060085671A1 Error indication in a raid memory system 失效
标题翻译：突袭存储系统中的错误指示
公开(公告)号：US20060085671A1
公开(公告)日：2006-04-20
申请号：US11291243
申请日：2005-12-01
申请人： Tim Majni , Gary Piccirillo , John MacLaren , Robert Lester , John Larson , Jerome Johnson , Benjamin Clark , Patrick Ferguson , Siamak Tavallaei , Jeffrey Autor , Christian Post , Dan Zink , Jeffery Galloway , Bret Roscoe
发明人： Tim Majni , Gary Piccirillo , John MacLaren , Robert Lester , John Larson , Jerome Johnson , Benjamin Clark , Patrick Ferguson , Siamak Tavallaei , Jeffrey Autor , Christian Post , Dan Zink , Jeffery Galloway , Bret Roscoe
IPC分类号： G06F11/00
CPC分类号： G06F11/328 , G06F11/108 , G06F11/1092 , G06F2211/1052
摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.
摘要翻译：计算机系统包括包含半导体存储器（诸如DIMM）的多个存储器模块。该系统包括主机/数据控制器，其利用XOR引擎以条带方式在多个存储器模块上存储数据和奇偶校验信息，以创建工业标准DIMM（RAID）的冗余阵列。主机/数据控制器还交织与多个存储器模块中的每一个相关联的多个通道上的数据。系统实施错误中断控制，ECC错误报告，响应命令错误的墨盒错误关闭程序，每个DIMM的未使用的段中的错误信息的存储，热插拔过程指示器和存储卡和DIMM的远程标记功能。

7. 发明授权

US5047000A Attachment for forming envelopes 失效
标题翻译：用于形成信封的附件
公开(公告)号：US5047000A
公开(公告)日：1991-09-10
申请号：US441363
申请日：1989-11-27
申请人： Robert Lester
发明人： Robert Lester
IPC分类号： B31B19/00
CPC分类号： B31B21/00 , B31B2221/10
摘要： A readily removable apparatus for use with an envelope blank-forming machine for the forming of envelopes from those blanks. The apparatus comprises an adhesive sprayer for applying adhesive on one side of a side flap of the envelope blank. It also includes an air lifter to lift a leading edge of the blank into engagement with a buckle bar. A plow folds the side flaps over a rear portion of the envelope blank, and rollers press the adhesive-covered side of the side flaps onto a rear portion of the blank to form an envelope.
摘要翻译：一种易于拆卸的装置，用于与这些坯料形成信封的信封坯料成形机一起使用。该装置包括用于在信封毛坯的侧翼的一侧上施加粘合剂的粘合剂喷涂器。它还包括一个空气提升器，用于提升坯件的前缘与一个带扣相配合。犁将侧翼折叠在信封坯料的后部上，并且辊将侧翼的粘合剂覆盖的侧面压到坯料的后部以形成信封。

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