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1. 发明申请

US20060072267A1 HIGH VOLTAGE ESD POWER CLAMP 失效
标题翻译：高电压ESD功率钳位
公开(公告)号：US20060072267A1
公开(公告)日：2006-04-06
申请号：US10711748
申请日：2004-10-01
申请人： Kiran Chatty , Robert Gauthier , Mahmoud Mousa , Mujahid Muhammad , Christopher Putnam
发明人： Kiran Chatty , Robert Gauthier , Mahmoud Mousa , Mujahid Muhammad , Christopher Putnam
IPC分类号： H03K19/0175
CPC分类号： H01L27/0266 , H03K17/08142
摘要： A structure and apparatus is provided for an electrostatic discharge power clamp, for use with high voltage power supplies. The power clamp includes a network of transistor devices, for example, nFETs arranged in series between a power rail and a ground rail. The first transistor device is biased into a partially on-state, and thus, neither device sees the full voltage potential between the power rail and the ground rail. Accordingly, the power clamp can function in voltage environments higher than the native voltage of the transistor devices. Additionally, the second transistor device is controlled by an RC network functioning as a trigger which allows the second transistor device to turn on during a voltage spike such as occurs during an ESD event. The capacitor of the RC network may be small thereby requiring small real estate on the integrated circuit. The clamp may have fast turn-on times as well as conducting current for long periods of time after turning on.
摘要翻译：为静电放电电源钳提供一种用于高压电源的结构和装置。功率钳包括晶体管器件网络，例如串联布置在电源轨和接地轨之间的nFET。第一晶体管器件被偏置成部分导通状态，因此，两个器件都不会看到电源轨和接地轨之间的全电压电位。因此，功率钳可以在高于晶体管器件的天然电压的电压环境中工作。此外，第二晶体管器件由用作触发器的RC网络来控制，该RC网络允许第二晶体管器件在诸如在ESD事件期间发生的电压尖峰期间导通。 RC网络的电容器可能很小，从而在集成电路上需要小的空间。打开后，夹具可能会导通快速导通时间，并长时间传导电流。

2. 发明申请

US20060226491A1 INVERTED MULTILAYER SEMICONDUCTOR DEVICE ASSEMBLY 失效
标题翻译：反相多层半导体器件组件
公开(公告)号：US20060226491A1
公开(公告)日：2006-10-12
申请号：US10907566
申请日：2005-04-06
申请人： Robert Gauthier , Mahmoud Mousa , Christopher Putnam
发明人： Robert Gauthier , Mahmoud Mousa , Christopher Putnam
IPC分类号： H01L29/04 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/76251 , H01L21/8221 , H01L21/823807 , H01L21/84 , H01L27/0688
摘要： An apparatus and method for an inverted multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device may be different than the active region of at least another device. Where the multilayer SOI device has a first layer including a PMOS device with a silicon active region having a crystal orientation of [100], the second layer may be an NMOS device with an active region having a silicon layer having a crystal orientation of [110]. The second layer is bonded to the first layer. The method and apparatus can be extended to more than two layers thus forming a multilayer SOI device having a different crystal orientation at each layer. The multiple layer SOI device may form circuits of reduced surface area.
摘要翻译：提供了一种用于倒置多层硅绝缘体（SOI）器件的装置和方法。在多层SOI器件中，器件的至少一个有源区的晶体取向可以不同于至少另一器件的有源区。在多层SOI器件具有包括具有[100]晶体取向的硅有源区的PMOS器件的第一层的情况下，第二层可以是具有晶体取向为[110]的具有硅层的有源区的NMOS器件 ]。第二层结合到第一层。该方法和装置可以扩展到两层以上，从而形成在每层具有不同晶体取向的多层SOI器件。多层SOI器件可形成表面积减小的电路。

3. 发明申请

US20070262345A1 ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME 有权
标题翻译：静电放电保护装置及其制造方法
公开(公告)号：US20070262345A1
公开(公告)日：2007-11-15
申请号：US11781370
申请日：2007-07-23
申请人： Robert Gauthier , Junjun Li , Souvick Mitra , Mahmoud Mousa , Christopher Putnam
发明人： Robert Gauthier , Junjun Li , Souvick Mitra , Mahmoud Mousa , Christopher Putnam
IPC分类号： H01L21/02 , H01L29/66
CPC分类号： H01L29/7436 , H01L21/84 , H01L27/0262 , H01L27/1203
摘要： A silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.
摘要翻译：硅控制整流器，制造硅控制整流器的方法和使用硅控制整流器作为集成电路的静电放电保护器件。硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为在平行于水平面的单个水平方向上。

4. 发明申请

US20070053120A1 APPARATUS AND METHOD FOR IMPROVED TRIGGERING AND LEAKAGE CURRENT CONTROL OF ESD CLAMPING DEVICES 失效
标题翻译： ESD钳位装置的改进触发和泄漏电流控制的装置和方法
公开(公告)号：US20070053120A1
公开(公告)日：2007-03-08
申请号：US11162198
申请日：2005-08-31
申请人： Robert Gauthier , Junjun Li , Souvick Mitra , Christopher Putnam
发明人： Robert Gauthier , Junjun Li , Souvick Mitra , Christopher Putnam
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： An apparatus for protecting an integrated circuit from an electrostatic discharge (ESD) event includes a multiple stage triggering network configured between a pair of power rails, and a power clamp coupled to the multiple stage triggering network, the power clamp configured to discharge current from the ESD event. The multiple stage triggering network has a first control path and a second control path configured to individually control activation of the power clamp.
摘要翻译：用于保护集成电路免受静电放电（ESD）事件的装置包括配置在一对电源轨之间的多级触发网络和耦合到多级触发网络的功率钳，该电源钳被配置为从 ESD事件。多级触发网络具有被配置为单独地控制功率钳的激活的第一控制路径和第二控制路径。

5. 发明申请

US20050227418A1 METHOD FOR CREATING A SELF-ALIGNED SOI DIODE BY REMOVING A POLYSILICON GATE DURING PROCESSING 失效
标题翻译：通过在加工过程中移除多晶硅栅极创建自对准SOI二极管的方法
公开(公告)号：US20050227418A1
公开(公告)日：2005-10-13
申请号：US10708912
申请日：2004-03-31
申请人： Kiran Chatty , Robert Gauthier , Mujahid Muhammad , Christopher Putnam
发明人： Kiran Chatty , Robert Gauthier , Mujahid Muhammad , Christopher Putnam
IPC分类号： H01L21/329 , H01L21/84 , H01L27/02 , H01L27/12 , H01L29/861
CPC分类号： H01L27/0255 , H01L21/84 , H01L27/1203 , H01L29/66136 , H01L29/861
摘要： A method of forming a self-aligned SOI diode, the method comprising depositing a protective structure over a substrate; implanting a plurality of diffusion regions of variable dopant types in an area between at least one pair of isolation regions in the substrate, the plurality of diffusion regions separated by a diode junction, wherein the implanting aligns an upper surface of the diode junction with the protective structure; and removing the protective structure. The method further comprises forming a silicide layer over the diffusion regions and aligned with the protective structure. The protective structure comprises a hard mask, wherein the hard mask comprises a silicon nitride layer. Alternatively, the protective structure comprises a polysilicon gate and insulating spacers on opposite sides of the gate. Furthermore, in the removing step, the spacers remain on the substrate.
摘要翻译：一种形成自对准SOI二极管的方法，所述方法包括在衬底上沉积保护结构; 在衬底中的至少一对隔离区域之间的区域中注入多个可变掺杂剂类型的扩散区域，所述多个扩散区域被二极管结点隔开，其中所述注入将所述二极管结的上表面与所述保护层结构体; 并移除保护结构。该方法还包括在扩散区上形成硅化物层并与保护结构对准。保护结构包括硬掩模，其中硬掩模包括氮化硅层。或者，保护结构包括在栅极的相对侧上的多晶硅栅极和绝缘间隔物。此外，在去除步骤中，衬垫保留在衬底上。

6. 发明申请

US20050068702A1 ELECTRO-STATIC DISCHARGE PROTECTION CIRCUIT 有权
标题翻译：电子放电保护电路
公开(公告)号：US20050068702A1
公开(公告)日：2005-03-31
申请号：US10605441
申请日：2003-09-30
申请人： John Connor , Robert Gauthier , Christopher Putnam , Alan Roberts
发明人： John Connor , Robert Gauthier , Christopher Putnam , Alan Roberts
IPC分类号： H01L27/02 , H02H9/00
CPC分类号： H01L27/0285
摘要： An ESD protection circuit including the following: one or more inverters (I1, I2, I3), each of the one or more inverters having an input and an output; an RC network (11) having an output node (RCT), output node (RCT) connected with the input of at least one of said one or more inverters; a clamping device (N3) joined with the output of at least one of one or more inverters (I1, I2, I3); and a feedback device (NKP) in communication with clamping device (N3) and output node (RCT) of RC network (11). An ESD protection circuit according to claim 7, wherein said RC network includes one or more resistors, and one or more decoupling capacitors. In one embodiment, feedback device (NKP) is an NFET and each of one or more inverters (I1, I2, I3) includes a PFET and NFET pair (P0/N0, P1/N1, P2/N2).
摘要翻译：一种ESD保护电路，包括：一个或多个逆变器（I1，I2，I3），所述一个或多个逆变器中的每一个具有输入和输出; 具有输出节点（RCT）的RC网络（11），与所述一个或多个逆变器中的至少一个的输入端连接的输出节点（RCT）与一个或多个逆变器（I1，I2，I3）中的至少一个的输出端连接的钳位装置（N3）; 以及与RC网络（11）的钳位装置（N3）和输出节点（RCT）通信的反馈装置（NKP）。 8.根据权利要求7所述的ESD保护电路，其中所述RC网络包括一个或多个电阻器和一个或多个去耦电容器。在一个实施例中，反馈装置（NKP）是NFET，并且一个或多个反相器（I1，I2，I3）中的每一个包括PFET和NFET对（P0 / N0，P1 / N1，P2 / N2）。

7. 发明申请

US20050045952A1 PFET-BASED ESD PROTECTION STRATEGY FOR IMPROVED EXTERNAL LATCH-UP ROBUSTNESS 审中-公开
标题翻译：基于PFET的ESD保护策略，用于改进外部锁定稳定性
公开(公告)号：US20050045952A1
公开(公告)日：2005-03-03
申请号：US10604922
申请日：2003-08-27
申请人： Kiran Chatty , Robert Gauthier , Mujahid Muhammad , Christopher Putnam
发明人： Kiran Chatty , Robert Gauthier , Mujahid Muhammad , Christopher Putnam
IPC分类号： H01L21/336 , H01L27/02
CPC分类号： H01L27/0266
摘要： A method and apparatus for protection against electrostatic discharge (ESD) with improved latch-up robustness featuring a silicide blocked p-type field effect transistor is disclosed. The transistor has a snapback voltage that is less than the breakdown voltage of its gate oxide. The transistor is part of an integrated circuit and coupled to an I/O pad having no n-diffusions connected directly to it. A given integrated circuit may employ one or more the transistors configured in accordance with the invention that are associated with one or more I/O pads within the integrated circuit.
摘要翻译：公开了一种具有改进的闩锁鲁棒性的防静电放电（ESD）的方法和装置，其具有硅化物阻挡的p型场效应晶体管。晶体管具有小于其栅极氧化物的击穿电压的快速恢复电压。晶体管是集成电路的一部分，并且耦合到没有直接连接到其的n扩散的I / O焊盘。给定的集成电路可以采用根据本发明配置的一个或多个与集成电路内的一个或多个I / O焊盘相关联的晶体管。

8. 发明申请

US20060157799A1 LOW TRIGGER VOLTAGE, LOW LEAKAGE ESD NFET 失效
标题翻译：低触发电压，低漏电ESD NFET
公开(公告)号：US20060157799A1
公开(公告)日：2006-07-20
申请号：US10905682
申请日：2005-01-17
申请人： Kiran Chatty , Robert Gauthier , Terence Hook , Christopher Putnam , Mujahid Muhammad
发明人： Kiran Chatty , Robert Gauthier , Terence Hook , Christopher Putnam , Mujahid Muhammad
IPC分类号： H01L29/76
CPC分类号： H01L29/78 , H01L27/027
摘要： A field effect transistor with associated parasitic lateral npn bipolar junction transistor includes a source region in a substrate, a channel region in the substrate laterally adjacent to the source region, a drain region in the substrate laterally adjacent to the channel region, and a gate above the channel region of the substrate. In addition, a reduced trigger voltage region of the substrate is positioned below the drain region. The reduced trigger voltage region has a threshold voltage of about zero and comprises an undoped region of the pure wafer substrate. Thus, the reduced trigger voltage region is free of implanted N-type and P-type doping.
摘要翻译：具有相关联的寄生横向npn双极结型晶体管的场效应晶体管包括衬底中的源极区域，与源极区域横向相邻的衬底中的沟道区域，衬底中的与沟道区域横向相邻的漏极区域，以及位于衬底的沟道区域。此外，衬底的降低的触发电压区域位于漏极区域的下方。降低的触发电压区域具有约零的阈值电压，并且包括纯晶片衬底的未掺杂区域。因此，降低的触发电压区域没有注入的N型和P型掺杂。

9. 发明申请

US20080050880A1 STRUCTURE FOR UNIFORM TRIGGERING OF MULTIFINGER SEMICONDUCTOR DEVICES WITH TUNABLE TRIGGER VOLTAGE 审中-公开
标题翻译：具有可调触发电压的多器件半导体器件均匀触发的结构
公开(公告)号：US20080050880A1
公开(公告)日：2008-02-28
申请号：US11931634
申请日：2007-10-31
申请人： Michel Abou-Khalil , Robert Gauthier , Hongmei Li , Junjun Li , Souvick Mitra , Christopher Putnam
发明人： Michel Abou-Khalil , Robert Gauthier , Hongmei Li , Junjun Li , Souvick Mitra , Christopher Putnam
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/41733 , H01L29/41775 , H01L29/458 , H01L29/6653 , H01L29/7833 , H01L29/78621 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of an MOS structure and then selectively plating a metallic or intermetallic material on exposed portions of a semiconductor substrate that were previously protected by the outer spacers. The present invention also provides a semiconductor structure that is formed utilizing the method. The semiconductor structure includes a low-resistance connection between the silicided source/drain regions and the channel regions which includes a selectively plated metallic or intermetallic material.
摘要翻译：本发明提供了一种方法，其中提供了与扩展离子注入工艺无关的MOS沟道和硅化源极/漏极区之间的低电阻连接以及器件重叠电容。本发明的方法广泛地包括选择性地去除MOS结构的外部间隔物，然后在先前由外部间隔物保护的半导体衬底的暴露部分上选择性地镀覆金属或金属间化合物。本发明还提供了利用该方法形成的半导体结构。半导体结构包括硅化源/漏区和沟道区之间的低电阻连接，其包括选择性镀金属或金属间化合物。

10. 发明申请

US20050224882A1 LOW TRIGGER VOLTAGE ESD NMOSFET TRIPLE-WELL CMOS DEVICES 审中-公开
标题翻译：低触发电压ESD NMOSFET三阱CMOS器件
公开(公告)号：US20050224882A1
公开(公告)日：2005-10-13
申请号：US10709041
申请日：2004-04-08
申请人： Kiran Chatty , Robert Gauthier , Mujahid Muhammad , Christopher Putnam
发明人： Kiran Chatty , Robert Gauthier , Mujahid Muhammad , Christopher Putnam
IPC分类号： H01L23/62 , H01L29/06 , H01L29/10 , H01L29/78
CPC分类号： H01L29/78 , H01L29/0653 , H01L29/1083 , H01L2924/0002 , H01L2924/00
摘要： An ESD NMOSFET, and a method for lowering a ESD NMOSFET trigger voltage. An ESD NMOSFET is configured in triple well CMOS architecture where the first well is separated from second and third wells by respective shallow well isolation regions. The first well is also separated from the substrate along the bottom by a conductive band region. A substrate contact is located outside of the first, second and third wells, and provides a current path during an ESD event from the first well. Source and drain regions are formed in the first well, to form an FET with the drain being connected to an I/O pad which is subject to an ESD event. A resistive path extends through an opening in the conductive band region to a substrate contact, providing an increased I/O pad to substrate resistance which decreases the trigger voltage for the ESD NMOSFET.
摘要翻译： ESD NMOSFET，以及降低ESD NMOSFET触发电压的方法。 ESD NMOSFET配置在三阱CMOS结构中，其中第一阱通过相应的浅阱隔离区与第二阱和第三阱分离。第一阱也通过导电带区沿着底部与衬底分离。衬底触点位于第一，第二和第三阱的外部，并且在来自第一阱的ESD事件期间提供电流路径。源极和漏极区域形成在第一阱中，以形成FET，其漏极连接到经受ESD事件的I / O焊盘。电阻路径延伸穿过导电带区域中的开口到衬底接触，从而为衬底电阻提供增加的I / O焊盘，从而降低ESD NMOSFET的触发电压。

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