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1. 发明授权

US06445607B2 Method for operating an integrated memory 失效
标题翻译：操作集成存储器的方法
公开(公告)号：US06445607B2
公开(公告)日：2002-09-03
申请号：US09829288
申请日：2001-04-09
申请人： Robert Esterl , Heinz Hönigschmid , Helmut Kandolf , Thomas Röhr
发明人： Robert Esterl , Heinz Hönigschmid , Helmut Kandolf , Thomas Röhr
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A description is given of a method for operating an integrated memory which has memory cells each having a selection transistor and a storage capacitor with a ferroelectric storage effect. The memory contains a plate line, which is connected to one of the column lines via a series circuit containing a selection transistor and a storage capacitor of respective memory cells. A memory access is carried out according to the “pulsed plate concept”. In this case, the temporal sequence is controlled in such a way that, in an access cycle, the storage capacitor of the memory cell to be selected is in each case charged and discharged by the same amount. An attenuation or destruction of the information stored in the memory cells, which is caused by source-drain leakage currents of unactivated selection transistors, is thus avoided.
摘要翻译：给出了一种用于操作具有存储单元的集成存储器的方法，每个存储单元都具有选择晶体管和具有铁电存储效应的存储电容器。存储器包含板线，其经由包含各个存储器单元的选择晶体管和存储电容器的串联电路连接到列线之一。根据“脉冲板概念”进行记忆存取。在这种情况下，以这样的方式控制时间序列，使得在访问周期中，要选择的存储单元的存储电容器在每种情况下都以相同的量被放电。因此避免了由未激活的选择晶体管的源漏泄漏电流引起的存储在存储单元中的信息的衰减或破坏。

2. 发明授权

US06515890B2 Integrated semiconductor memory having memory cells with a ferroelectric memory property 有权
标题翻译：具有具有铁电存储器特性的存储单元的集成半导体存储器
公开(公告)号：US06515890B2
公开(公告)日：2003-02-04
申请号：US09780305
申请日：2001-02-09
申请人： Robert Esterl , Helmut Kandolf , Heinz Hönigschmid , Thomas Röhr
发明人： Robert Esterl , Helmut Kandolf , Heinz Hönigschmid , Thomas Röhr
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： An integrated semiconductor memory has memory cells with a ferroelectric memory property. The memory cells are in each case connected between a column line and a charge line. The column line is connected to a read amplifier which supplies an output signal. The charge line is connected to a driver circuit which provides the charge line with a given potential. In an inactive mode, the column line and the charge line are jointly connected to a connection for a common supply potential in the read amplifier or in the driver circuit. As a result, a relatively quick equalization of a potential between the lines is possible. Thus, unintended changes in the memory cell content due to interfering voltages are avoided.
摘要翻译：集成半导体存储器具有具有铁电存储器特性的存储单元。存储器单元在每种情况下都连接在列线和充电线之间。列线连接到提供输出信号的读取放大器。充电线连接到向给定电位提供充电线的驱动器电路。在非活动模式下，列线和充电线在读取放大器或驱动电路中共同连接到用于共同供电电位的连接。结果，线之间的电位的相对快速的均衡是可能的。因此，避免了由于干扰电压引起的存储器单元内容的意外变化。

3. 发明授权

US06577528B2 Circuit configuration for controlling write and read operations in a magnetoresistive memory configuration 失效
公开(公告)号：US06577528B2
公开(公告)日：2003-06-10
申请号：US10023155
申请日：2001-12-17
申请人： Dietmar Gogl , Helmut Kandolf , Heinz Hönigschmid
发明人： Dietmar Gogl , Helmut Kandolf , Heinz Hönigschmid
IPC分类号： G11C1100
CPC分类号： G11C8/12 , G11C11/15
摘要： A circuit configuration for controlling write operations and read operations in an MRAM memory configuration includes selection transistors grouped in sections of equal numbers of the selection transistors. The selection transistors of each of the sections are jointly connected, at the ends of the bit lines, to a respective interacting pair of read/write amplifiers via those electrode terminals of the selection transistors that are not connected to the bit lines. The read/write amplifiers are controlled such that if a write signal is fed thereto, write currents for writing a logic “1” or “0” flow in a first direction or a second direction in all of the bit lines selected by a corresponding column select signal and, if a read signal is fed in, a logic state stored in one of the magnetoresistive memory cells can be read out.

4. 发明授权

US06816406B2 Magnetic memory configuration 有权
标题翻译：磁记忆体配置
公开(公告)号：US06816406B2
公开(公告)日：2004-11-09
申请号：US10715023
申请日：2003-11-17
申请人： Heinz Hönigschmid , Helmut Kandolf , Stefan Lammers
发明人： Heinz Hönigschmid , Helmut Kandolf , Stefan Lammers
IPC分类号： G11C1114
CPC分类号： G11C11/16
摘要： A magnetic memory configuration stores data and avoids ageing effects. The memory configuration contains a cell array containing magnetic memory cells disposed along a first direction and a second direction crossing the former, a multiplicity of electrical lines along the first direction, and a multiplicity of electrical lines along the second direction. The magnetic memory cells in each case are disposed at crossover points of the electrical lines. A first current supply device supplies respectively selected electrical lines along the first direction with current. A second current supply device supplies respectively selected electrical lines along the second direction with current. The second current supply device is configured for setting the direction of the current in accordance with an information item to be written. The first current supply device is suitable for changing over the direction of the current as desired.

5. 发明授权

US06657916B2 Integrated memory with memory cell array 有权
标题翻译：集成存储器与存储单元阵列
公开(公告)号：US06657916B2
公开(公告)日：2003-12-02
申请号：US10054195
申请日：2002-01-22
申请人： Heinz Hönigschmid , Stefan Lammers , Helmut Kandolf
发明人： Heinz Hönigschmid , Stefan Lammers , Helmut Kandolf
IPC分类号： G11C800
CPC分类号： G11C8/00 , G11C8/08
摘要： An integrated memory has a memory cell array with memory cells which are connected to word lines and bit lines. For the purpose of reading from or writing to one of the memory cells, a first word line can be connected to a supply circuit via a controllable first switching device and a second word line can be connected to the supply circuit via a controllable second switching device. A control circuit can drive the first switching device in dependence of an activation state of the second word line and the second switching device in dependence of an activation state of the first word line. Consequently, existing word lines that are not currently being used can be used for addressing one of the memory cells. As a result, only one wiring plane is required for the word lines.
摘要翻译：集成存储器具有存储单元阵列，其存储单元连接到字线和位线。为了从一个存储单元读取或写入存储单元，第一字线可以通过可控的第一开关器件连接到电源电路，并且第二字线可以经由可控的第二开关器件连接到电源电路。根据第一字线的激活状态，控制电路可以根据第二字线和第二开关器件的激活状态来驱动第一开关器件。因此，当前未使用的现有字线可用于寻址存储单元之一。结果，字线只需要一个接线面。

6. 发明授权

US06664158B2 Ferroelectric memory configuration and a method for producing the configuration 有权
公开(公告)号：US06664158B2
公开(公告)日：2003-12-16
申请号：US10034931
申请日：2001-11-21
申请人： Christine Dehm , Heinz Hönigschmid , Thomas Röhr
发明人： Christine Dehm , Heinz Hönigschmid , Thomas Röhr
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L27/11507
摘要： An integrated ferroelectric memory configuration and a method for producing the integrated ferroelectric memory configuration, in which memory cells are arranged using the stacking principle, and both capacitor electrodes, which are located one above the other, of each memory cell are directly electrically connected by means of contact plugs to corresponding source and drain regions of an associated selection transistor in the substrate. Contact plugs for the contact connection to the upper capacitor electrodes are produced from above the configuration.

7. 发明授权

US06480055B2 Decoder element for generating an output signal having three different potentials and an operating method for the decoder element 有权
标题翻译：用于产生具有三个不同电位的输出信号的解码器元件和用于解码器元件的操作方法
公开(公告)号：US06480055B2
公开(公告)日：2002-11-12
申请号：US09822028
申请日：2001-03-29
申请人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Ernst Neuhold , Thomas Röhr
发明人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Ernst Neuhold , Thomas Röhr
IPC分类号： H03K1776
CPC分类号： G11C5/143 , G11C8/08 , G11C16/12 , H03K19/09425 , H03M5/16
摘要： A decoder element is provided with an output, whereby an output signal with one of three different possible potentials is produced. The output signal may have a value of either a first potential, a second potential, and a third potential, where the second potential lies between the first potential and the third potential. The output signal is produced according to voltage values of input signals at terminal connections of the decoder element.
摘要翻译：解码器元件设置有输出，由此产生具有三种不同可能电位之一的输出信号。输出信号可以具有第一电位，第二电位和第三电位的值，其中第二电位位于第一电位和第三电位之间。输出信号根据解码器元件的端子连接处的输入信号的电压值而产生。

8. 发明授权

US06803618B2 MRAM configuration having selection transistors with a large channel width 有权
标题翻译： MRAM配置具有具有大通道宽度的选择晶体管
公开(公告)号：US06803618B2
公开(公告)日：2004-10-12
申请号：US10436723
申请日：2003-05-13
申请人： Heinz Hönigschmid , Thomas Böhm , Thomas Röhr
发明人： Heinz Hönigschmid , Thomas Böhm , Thomas Röhr
IPC分类号： H01L2976
CPC分类号： G11C11/16
摘要： The invention relates to an MRAM configuration that includes a selection transistor connected to several MTJ memory cells. The selection transistor has an increased channel width.
摘要翻译：本发明涉及一种MRAM配置，其包括连接到多个MTJ存储器单元的选择晶体管。选择晶体管具有增加的沟道宽度。

9. 发明授权

US06525974B2 Integrated memory with redundancy 有权
公开(公告)号：US06525974B2
公开(公告)日：2003-02-25
申请号：US09888023
申请日：2001-06-22
申请人： Ernst Neuhold , Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Thomas Böhm , Thomas Röhr
发明人： Ernst Neuhold , Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Thomas Böhm , Thomas Röhr
IPC分类号： G11C700
CPC分类号： G11C29/808 , G11C29/846
摘要： An integrated memory contains two normal read amplifiers and two first redundant read amplifiers. It also contains bit lines which are combined into at least two individually addressable normal columns, at least one of which from each normal column is connected to one of the normal read amplifiers. It also has first redundant bit lines which are combined into one individually addressable redundant column, at least one of which is connected to one of the redundant read amplifiers. The first redundant read amplifier and its redundant columns are provided for replacing the two normal read amplifiers and one of the normal columns.

10. 发明授权

US06459626B1 Integrated memory having memory cells and reference cells, and corresponding operating method 有权
公开(公告)号：US06459626B1
公开(公告)日：2002-10-01
申请号：US09962703
申请日：2001-09-24
申请人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Thomas Röhr
发明人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Thomas Röhr
IPC分类号： G11C700
CPC分类号： G11C7/14 , G11C11/22
摘要： An integrated memory has two first switching elements, which respectively connect a bit line of a first bit line pair to a bit line of a second bit line pair. In addition, the integrated memory has two second switching elements, which respectively connect one of the reference cells of one bit line pair to that bit line of the other bit line pair which is not connected via the corresponding first switching element to the bit line assigned to this reference cell. Information is written back to the reference cells via the sense amplifiers. A method of operating the integrated memory is also provided.

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