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1. 发明授权

US5155563A Semiconductor device having low source inductance 失效
标题翻译：具有低源电感的半导体器件
公开(公告)号：US5155563A
公开(公告)日：1992-10-13
申请号：US670654
申请日：1991-03-18
申请人： Robert B. Davies , Robert J. Johnsen , Francine Y. Robb
发明人： Robert B. Davies , Robert J. Johnsen , Francine Y. Robb
IPC分类号： H01L29/78 , H01L21/74 , H01L29/10 , H01L29/417
CPC分类号： H01L29/4175 , H01L21/743 , H01L29/1087 , H01L29/7835
摘要： A semiconductor device having a low source inductance are fabricated by having a maximum of two sources each in contact with a region which makes contact to a substrate or back side of the device. The back side source contact also allows the device to be mounted directly to a grounded heatsink.
摘要翻译：具有低源电感的半导体器件通过具有最多两个源来制造，每个源与与器件的衬底或背面接触的区域接触。背面源触点也允许器件直接安装在接地散热器上。

2. 发明授权

US08093133B2 Transient voltage suppressor and methods 有权
标题翻译：瞬态电压抑制器及方法
公开(公告)号：US08093133B2
公开(公告)日：2012-01-10
申请号：US12098369
申请日：2008-04-04
申请人： Emmanuel Saucedo-Flores , Mingjiao Liu , Francine Y. Robb , Ali Salih
发明人： Emmanuel Saucedo-Flores , Mingjiao Liu , Francine Y. Robb , Ali Salih
IPC分类号： H01L21/20
CPC分类号： H01L29/87 , H01L29/747 , H01L29/866
摘要： Transient voltage suppressor and method for manufacturing the transient voltage suppressor having a dopant or carrier concentration in a portion of a gate region near a Zener region that is different from a dopant concentration in a portion of a gate region that is away from the Zener region.
摘要翻译：瞬态电压抑制器和制造瞬态电压抑制器的方法，该电压抑制器在齐纳一区域附近的栅极区域的与偏离齐纳一区域的栅极区域的一部分中的掺杂浓度不同的部分中具有掺杂剂或载流子浓度。

3. 发明授权

US07714381B2 Method of forming an integrated power device and structure 有权
标题翻译：形成集成电力装置和结构的方法
公开(公告)号：US07714381B2
公开(公告)日：2010-05-11
申请号：US11095135
申请日：2005-04-01
申请人： Francine Y. Robb , Stephen P. Robb , Prasad Venkatraman , Zia Hossain
发明人： Francine Y. Robb , Stephen P. Robb , Prasad Venkatraman , Zia Hossain
IPC分类号： H01L27/105
CPC分类号： H01L29/7813 , H01L21/823487 , H01L21/823885 , H01L27/088 , H01L27/0922 , H01L29/0878 , H01L29/66734
摘要： In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.
摘要翻译：在一个实施例中，在具有其它晶体管的半导体衬底上形成垂直功率晶体管。垂直功率晶体管下面的半导体层的一部分被掺杂以为垂直功率晶体管提供低导通电阻。

4. 发明申请

US20090250720A1 TRANSIENT VOLTAGE SUPPRESSOR AND METHODS 有权
标题翻译：瞬态电压抑制器和方法
公开(公告)号：US20090250720A1
公开(公告)日：2009-10-08
申请号：US12098369
申请日：2008-04-04
申请人： Emmanuel Saucedo-Flores , Mingjiao Liu , Francine Y. Robb , Ali Salih
发明人： Emmanuel Saucedo-Flores , Mingjiao Liu , Francine Y. Robb , Ali Salih
IPC分类号： H01L29/866 , H01L21/20
CPC分类号： H01L29/87 , H01L29/747 , H01L29/866
摘要： Transient voltage suppressor and method for manufacturing the transient voltage suppressor having a dopant or carrier concentration in a portion of a gate region near a Zener region that is different from a dopant concentration in a portion of a gate region that is away from the Zener region.
摘要翻译：瞬态电压抑制器和制造瞬态电压抑制器的方法，该电压抑制器在齐纳一区域附近的栅极区域的与偏离齐纳一区域的栅极区域的一部分中的掺杂浓度不同的部分中具有掺杂剂或载流子浓度。

5. 发明申请

US20090162988A1 METHOD OF FORMING LOW CAPACITANCE ESD DEVICE AND STRUCTURE THEREFOR 有权
公开(公告)号：US20090162988A1
公开(公告)日：2009-06-25
申请号：US12395076
申请日：2009-02-27
申请人： Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, JR. , George Chang
发明人： Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, JR. , George Chang
IPC分类号： H01L21/77 , H01L21/762
CPC分类号： H01L29/8613 , H01L27/0255 , H01L29/8618 , Y10S257/929 , Y10S438/966 , Y10S438/983
摘要： In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.

6. 发明授权

US07537970B2 Bi-directional transistor with by-pass path and method therefor 有权
标题翻译：具有旁路的双向晶体管及其方法
公开(公告)号：US07537970B2
公开(公告)日：2009-05-26
申请号：US11367626
申请日：2006-03-06
申请人： Francine Y. Robb , Stephen P. Robb
发明人： Francine Y. Robb , Stephen P. Robb
IPC分类号： H01L21/332
CPC分类号： H03K17/063 , H01L21/823487 , H01L21/823885 , H01L27/088 , H01L27/0922 , H03K17/687 , H03K2217/0018
摘要： In one embodiment, a transistor is formed to have a first current flow path to selectively conduct current in both directions through the transistor and to have a second current flow path to selectively conduct current in one direction.
摘要翻译：在一个实施例中，晶体管形成为具有第一电流流动路径，以选择性地在两个方向上导通电流通过晶体管，并且具有第二电流流动路径以选择性地在一个方向上导通电流。

7. 发明申请

US20080277694A1 SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE 有权
标题翻译：半导体元件及其制造方法
公开(公告)号：US20080277694A1
公开(公告)日：2008-11-13
申请号：US11746437
申请日：2007-05-09
申请人： Zia Hossain , Francine Y. Robb , Prasad Venkatraman
发明人： Zia Hossain , Francine Y. Robb , Prasad Venkatraman
IPC分类号： H01L27/095 , H01L21/44 , H01L29/76
CPC分类号： H01L27/0629 , H01L21/28512 , H01L21/28518 , H01L21/28537 , H01L21/76855 , H01L21/76895 , H01L21/8249
摘要： A semiconductor component that includes a Schottky device, an edge termination structure, a non-Schottky semiconductor device, combinations thereof and a method of manufacturing the semiconductor component. A semiconductor material includes a first epitaxial layer disposed on a semiconductor substrate and a second epitaxial layer disposed on the first epitaxial layer. The second epitaxial layer has a higher resistivity than the semiconductor substrate. A Schottky device and a non-Schottky semiconductor device are manufactured from the second epitaxial layer. In accordance with another embodiment, a semiconductor material includes an epitaxial layer disposed over a semiconductor substrate. The epitaxial layer has a higher resistivity than the semiconductor substrate. A doped region is formed in the epitaxial layer. A Schottky device and a non-Schottky semiconductor device are manufactured from the epitaxial layer.
摘要翻译：一种包括肖特基器件，边缘端接结构，非肖特基半导体器件及其组合的半导体部件和制造半导体部件的方法。半导体材料包括设置在半导体衬底上的第一外延层和设置在第一外延层上的第二外延层。第二外延层具有比半导体衬底更高的电阻率。由第二外延层制造肖特基器件和非肖特基半导体器件。根据另一实施例，半导体材料包括设置在半导体衬底上的外延层。外延层具有比半导体衬底更高的电阻率。在外延层中形成掺杂区域。由外延层制造肖特基器件和非肖特基半导体器件。

8. 发明申请

US20080258210A1 SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE 有权
标题翻译：半导体元件及其制造方法
公开(公告)号：US20080258210A1
公开(公告)日：2008-10-23
申请号：US11737923
申请日：2007-04-20
申请人： Prasad Venkatraman , Gordon M. Grivna , Francine Y. Robb , George Chang , Carroll Casteel
发明人： Prasad Venkatraman , Gordon M. Grivna , Francine Y. Robb , George Chang , Carroll Casteel
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0696 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.
摘要翻译：能够抑制寄生双极型晶体管的形成的半导体元件和使用减少数量的掩模步骤来制造半导体元件的方法。提供具有P型导电性区域的N型导电性的半导体材料。在P型导电性区域形成N型导电性的掺杂区域。沟槽形成在半导体材料中并延伸通过N型和P型导电性的区域。由半导体材料形成场氧化物，使得沟槽的部分在场氧化物的下方延伸。场氧化物在源区的形成中用作注入掩模。主体接触区域由半导体材料形成，并且形成与源区和身体区域接触的电导体。形成与半导体材料的背面接触的电导体。

9. 发明授权

US07282406B2 Method of forming an MOS transistor and structure therefor 有权
标题翻译：一种形成MOS晶体管的方法及其结构
公开(公告)号：US07282406B2
公开(公告)日：2007-10-16
申请号：US11367627
申请日：2006-03-06
申请人： Gordon M. Grivna , Francine Y. Robb
发明人： Gordon M. Grivna , Francine Y. Robb
IPC分类号： H01L21/8242
CPC分类号： H01L29/7813 , H01L21/823462 , H01L21/823857 , H01L27/088 , H01L27/0922 , H01L29/086 , H01L29/0878 , H01L29/4236 , H01L29/42368 , H01L29/66734 , H01L29/7803
摘要： In one embodiment, an MOS transistor is formed with trench gates. The gate structure of the trench gates generally has a first insulator that has a first thickness in one region of the gate and a second thickness in a second region of the gate.
摘要翻译：在一个实施例中，MOS晶体管形成有沟槽栅极。沟槽栅极的栅极结构通常具有在栅极的一个区域中具有第一厚度的第一绝缘体，并且在栅极的第二区域中具有第二厚度。

10. 发明授权

US4601778A Maskless etching of polysilicon 失效
标题翻译：无掩模蚀刻多晶硅
公开(公告)号：US4601778A
公开(公告)日：1986-07-22
申请号：US705161
申请日：1985-02-25
申请人： Francine Y. Robb
发明人： Francine Y. Robb
IPC分类号： H01L21/302 , H01L21/3213 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/32137 , Y10S438/924
摘要： Maskless etching of polysilicon is accomplished by exposing portions of a polysilicon surface to ion bombardment. Bombardment by oxygen or hydrogen ions is effective to reduce the etch rate of polysilicon in a chlorine-containing plasma. Therefore, patterned ion bombardment prior to etching in a chlorine plasma is effective to pattern the polysilicon surface.
摘要翻译：通过将多晶硅表面的部分暴露于离子轰击来实现多晶硅的无掩模蚀刻。通过氧或氢离子的轰击对于降低含氯等离子体中的多晶硅的蚀刻速率是有效的。因此，在氯等离子体中蚀刻之前的图案化离子轰击有效地对多晶硅表面进行图案化。

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