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1. 发明授权

US07584567B1 Hand guard assembly for firearms 有权
标题翻译：枪支手枪组件
公开(公告)号：US07584567B1
公开(公告)日：2009-09-08
申请号：US12110304
申请日：2008-04-26
申请人： Frank DeSomma , Robert B. Davies
发明人： Frank DeSomma , Robert B. Davies
IPC分类号： F41C23/16
CPC分类号： F41G11/003 , F41C23/16
摘要： A hand guard assembly for a firearm including a barrel. The assembly includes a tubular unitary body mounted to surround a portion of the barrel substantially coaxially and in a transversely spaced relationship. The tubular body includes a plurality of air flow openings formed therethrough and at least one of a top rail formed as a unitary portion of the tubular body and extending rearwardly along an upper portion of a receiver of the firearm, side accessory rails formed as a unitary portion of the tubular body and on opposed sides of the tubular body, and a bottom accessory rail formed as a unitary portion of the tubular body and on a bottom surface of the tubular body. In the preferred method of fabricating the assembly, the body and any include accessory rails are extruded.
摘要翻译：用于包括枪管的枪支的护手组件。该组件包括一个管状整体，其安装成围绕筒的一部分基本同轴并以横向间隔的关系。管状体包括多个通过其形成的空气流动开口，以及形成为管状体的整体部分的顶部轨道中的至少一个，并且沿着枪械的接收器的上部向后延伸，侧部辅助导轨形成为整体管状体的一部分和管状体的相对侧，以及形成为管状体的整体部分和管状体的底表面的底部辅助轨道。在制造组件的优选方法中，主体和任何包括的附件轨道被挤压。

2. 发明申请

US20080265313A1 SEMICONDUCTOR DEVICE HAVING ENHANCED PERFORMANCE AND METHOD 有权
标题翻译：具有增强性能和方法的半导体器件
公开(公告)号：US20080265313A1
公开(公告)日：2008-10-30
申请号：US12131295
申请日：2008-06-02
申请人： Gary H. Loechelt , Robert B. Davies , David H. Lutz
发明人： Gary H. Loechelt , Robert B. Davies , David H. Lutz
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7802 , H01L21/26586 , H01L21/2815 , H01L29/0878 , H01L29/402 , H01L29/42368 , H01L29/42376 , H01L29/66719 , H01L29/66727
摘要： In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a localized region of doping near a portion of a channel region where current exits during operation.
摘要翻译：在一个实施例中，半导体器件形成在半导体材料体中。半导体器件包括在操作期间电流离开的沟道区域的一部分附近的局部化掺杂区域。

3. 发明授权

US07397084B2 Semiconductor device having enhanced performance and method 有权
标题翻译：具有增强的性能和方法的半导体器件
公开(公告)号：US07397084B2
公开(公告)日：2008-07-08
申请号：US11095136
申请日：2005-04-01
申请人： Gary H. Loechelt , Robert B. Davies , David H. Lutz
发明人： Gary H. Loechelt , Robert B. Davies , David H. Lutz
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L21/26586 , H01L21/2815 , H01L29/0878 , H01L29/402 , H01L29/42368 , H01L29/42376 , H01L29/66719 , H01L29/66727
摘要： In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a localized region of doping near a portion of a channel region where current exits during operation.
摘要翻译：在一个实施例中，半导体器件形成在半导体材料体中。半导体器件包括在操作期间电流离开的沟道区域的一部分附近的局部化掺杂区域。

4. 发明授权

US07148553B1 Semiconductor device with inductive component and method of making 有权
公开(公告)号：US07148553B1
公开(公告)日：2006-12-12
申请号：US09920222
申请日：2001-08-01
申请人： Robert B. Davies
发明人： Robert B. Davies
IPC分类号： H01L37/00
CPC分类号： H01L28/10 , H01F17/0006 , H01L23/5227 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit (10) includes a semiconductor substrate (11) that has a top surface (32) for forming a dielectric region (14) with a trench (40) and one or more adjacent cavities (16). A conductive material such as copper is disposed within the trench to produce an inductor (50). A top surface (49) of the inductor is substantially coplanar with an interconnect surface (31) of the semiconductor substrate, which facilitates connecting to the inductor with standard integrated circuit metallization (57).

5. 发明授权

US6051456A Semiconductor component and method of manufacture 失效
标题翻译：半导体元件及制造方法
公开(公告)号：US6051456A
公开(公告)日：2000-04-18
申请号：US216990
申请日：1998-12-21
申请人： Robert B. Davies , Andreas A. Wild
发明人： Robert B. Davies , Andreas A. Wild
IPC分类号： H01L21/331 , H01L21/336 , H01L21/8222 , H01L21/8238 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L27/092 , H01L29/732 , H01L29/78 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/0623 , H01L21/8249
摘要： A semiconductor component includes an asymmetric transistor having two lightly doped drain regions (1300, 1701), a channel region (1702), a source region (1916) located within the channel region (1702), a drain region located outside the channel region (1702), a dielectric structure (1404) located over at least one of the two lightly doped drain regions (1300, 1701), two gate electrodes (1902, 1903) located at opposite sides of the dielectric structure (1404), a drain electrode (1901) overlying the drain region (1915), and a source electrode (1904) overlying the source region (1916). The semiconductor component also includes another transistor having an emitter electrode (122) located between a base electrode (121) and a collector electrode (123) where the base electrode (121) is formed over a dielectric structure (1405).
摘要翻译：半导体部件包括具有两个轻掺杂漏极区域（1300,1701），沟道区域（1702），位于沟道区域（1702）内的源极区域（1916））的不对称晶体管，位于沟道区域外部的漏极区域 1702），位于两个轻掺杂漏极区（1300,1701）中的至少一个上的电介质结构（1404），位于电介质结构（1404）的相对侧的两个栅电极（1902,1903），漏电极（1901）和覆盖源区（1916）的源电极（1904）。该半导体元件还包括另一晶体管，其具有位于介电结构（1405）之间形成基极（121）的基极（121）和集电极（123）之间的发射极（122）。

6. 发明授权

US5879999A Method of manufacturing an insulated gate semiconductor device having a spacer extension 失效
标题翻译：具有间隔物延伸部的绝缘栅半导体器件的制造方法
公开(公告)号：US5879999A
公开(公告)日：1999-03-09
申请号：US720510
申请日：1996-09-30
申请人： Heemyong Park , Vida Ilderem , Robert B. Davies
发明人： Heemyong Park , Vida Ilderem , Robert B. Davies
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/28114 , H01L21/2815 , H01L29/42376 , H01L29/6656 , H01L29/7836
摘要： An insulated gate semiconductor device (10) having a gate structure (45) that includes a conductive spacer (32) and an extension region (46) extending from the conductive spacer (32). To form the gate structure (45), a stack having sidewalls (22) is formed over a major surface (12) of a semiconductor substrate (11). A gate dielectric (23) is then formed over the major surface (12) adjacent to the sidewalls (22). The conductive spacer (32) is formed on the gate dielectric (23). The extension region (46) is then formed using selective growth or deposition and patterning of polysilicon adjacent the conductive spacer (32).
摘要翻译：一种具有栅极结构（45）的绝缘栅极半导体器件（10），其包括导电间隔物（32）和从导电间隔物（32）延伸的延伸区域（46）。为了形成栅极结构（45），在半导体衬底（11）的主表面（12）上形成具有侧壁（22）的叠层。然后在与侧壁（22）相邻的主表面（12）上形成栅极电介质（23）。导电间隔物（32）形成在栅极电介质（23）上。然后使用与导电间隔物（32）相邻的多晶硅的选择性生长或沉积和图案化形成延伸区（46）。

7. 发明授权

US5661048A Method of making an insulated gate semiconductor device 失效
标题翻译：制造绝缘栅半导体器件的方法
公开(公告)号：US5661048A
公开(公告)日：1997-08-26
申请号：US408654
申请日：1995-03-21
申请人： Robert B. Davies , Chandrasekhara Sudhama , Frank K. Baker
发明人： Robert B. Davies , Chandrasekhara Sudhama , Frank K. Baker
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/10 , H01L29/423 , H01L29/49 , H01L29/78 , H01L21/265
CPC分类号： H01L29/4983 , H01L21/823857 , H01L29/1083 , H01L29/42376 , H01L29/4991 , H01L29/66659 , H01L29/7835
摘要： An insulated gate field effect transistor (10) having a reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor substrate (11) and a drain extension region (25) is formed in the dopant well (13). An oxide layer (26) is formed on the dopant well (13) wherein the oxide layer (26) has a thickness of at least 400 angstroms. A gate structure (61) having a gate shunt portion (32) over a thinned portion of the oxide (26) and a gate extension portion (58) over an unthinned portion of the oxide (26). The thinned portion of the oxide (26) forms a gate oxide of the field effect transistor (10) and the unthinned portion lowers a capacitance of the gate shunt portion (32) of the field effect transistor (10).
摘要翻译：具有减小的栅极 - 漏极电容的绝缘栅场效应晶体管（10）和制造场效应晶体管（10）的方法。掺杂剂阱（13）形成在半导体衬底（11）中，并且在掺杂剂阱（13）中形成漏极延伸区域（25）。氧化物层（26）形成在掺杂剂阱（13）上，其中氧化物层（26）具有至少400埃的厚度。栅极结构（61）具有在氧化物（26）的薄化部分上方的栅极分流部分（32）和位于氧化物（26）的未固化部分上的栅极延伸部分（58）。氧化物（26）的减薄部分形成场效应晶体管（10）的栅极氧化物，并且未固化部分降低场效应晶体管（10）的栅极分流部分（32）的电容。

8. 发明授权

US5451806A Method and device for sensing a surface temperature of an insulated gate semiconductor device 失效
标题翻译：用于感测绝缘栅极半导体器件的表面温度的方法和装置
公开(公告)号：US5451806A
公开(公告)日：1995-09-19
申请号：US205238
申请日：1994-03-03
申请人： Robert B. Davies
发明人： Robert B. Davies
IPC分类号： H01L27/02 , H01L27/07 , H01L29/78 , H01L23/56 , H01L29/66
CPC分类号： H01L29/7803 , H01L27/0211 , H01L27/07 , H01L2924/0002
摘要： A temperature sensing insulated gate semiconductor device (10) and method of using the insulated the insulated gate semiconductor device (10) for sensing a surface temperature. A lateral PNP bipolar transistor (63) is connected to a drain conductor (58) of an insulated gate field effect transistor (56). The insulated gate field effect transistor (56) is turned on, thereby shorting a collector conductor (64) with a base conductor (62) to form a diode connected lateral PNP bipolar transistor (63). A forward voltage is measured across an emitter-base junction of the diode connected lateral PNP bipolar transistor (63). The surface temperature of the insulated gate semiconductor device (10) is derived using the diode equation in conjunction with the current (67) and the forward voltage drop.
摘要翻译：一种温度感测绝缘栅极半导体器件（10）以及使用绝缘的绝缘栅极半导体器件（10）来感测表面温度的方法。横向PNP双极晶体管（63）连接到绝缘栅场效应晶体管（56）的漏极导体（58）。绝缘栅场效应晶体管（56）导通，由此用基极导体（62）短路集电极导体（64），形成二极管连接的横向PNP双极晶体管（63）。在二极管连接的横向PNP双极晶体管（63）的发射极 - 基极结两端测量正向电压。绝缘栅半导体器件（10）的表面温度是使用二极管方程结合电流（67）和正向压降导出的。

9. 发明授权

US5281839A Semiconductor device having a short gate length 失效
标题翻译：具有短栅极长度的半导体器件
公开(公告)号：US5281839A
公开(公告)日：1994-01-25
申请号：US52856
申请日：1993-04-23
申请人： Bertrand F. Cambou , Robert B. Davies
发明人： Bertrand F. Cambou , Robert B. Davies
IPC分类号： H01L21/285 , H01L21/338 , H01L29/10 , H01L29/812 , H01L29/20 , H01L29/22
CPC分类号： H01L29/66878 , H01L21/28587 , H01L21/28593 , H01L29/1029 , H01L29/812
摘要： A semiconductor device having a channel region having a first and a second portion. The first and second portions of the channel region are designed so that only a small portion is substantially depleted during operation. Thus, a semiconductor device having a short gate length is fabricated.
摘要翻译：一种半导体器件，具有具有第一和第二部分的沟道区。通道区域的第一和第二部分被设计成使得在操作期间只有一小部分被大量耗尽。因此，制造具有短栅极长度的半导体器件。

10. 发明授权

US5032878A High voltage planar edge termination using a punch-through retarding implant 失效
标题翻译：使用穿通延迟植入物的高压平面边缘终端
公开(公告)号：US5032878A
公开(公告)日：1991-07-16
申请号：US459506
申请日：1990-01-02
申请人： Robert B. Davies , Lowell E. Clark , David N. Okada
发明人： Robert B. Davies , Lowell E. Clark , David N. Okada
IPC分类号： H01L29/73 , H01L21/331 , H01L29/06 , H01L29/40 , H01L29/78
CPC分类号： H01L29/404 , H01L29/0619
摘要： A high voltage semiconductor structure having multiple guard rings, wherein guard rings farthest from a main junction are spaced further from each other than are guard rings closer to the main junction is provided. An enhancement region, which is of an opposite conductivity type from the guard rings, is formed between the guard rings to increase punch-through voltage between the guard rings, thereby increasing the breakdown voltage of the device. The enhancement region and close guard ring spacing result in a fine gradation of electric field and high punch-through breakdown voltage between guard rings.

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