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1. 发明申请

US20070245283A1 MINIMUM LAYOUT PERTURBATION-BASED ARTWORK LEGALIZATION WITH GRID CONSTRAINTS FOR HIERARCHICAL DESIGNS 失效
标题翻译：用于分层设计的网格约束的最小布局基于假设的艺术品法规
公开(公告)号：US20070245283A1
公开(公告)日：2007-10-18
申请号：US11279758
申请日：2006-04-14
申请人： Robert Allen , Michael Gray , Fuok-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker
发明人： Robert Allen , Michael Gray , Fuok-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method comprises extracting a hierarchical grid constraint set and modeling one or more critical objects of at least one cell as a variable set. The method further comprises solving a linear programming problem based on the hierarchical grid constraint set with the variable set to provide initial locations of the critical objects of the at least one cell and determining target on-grid locations of the one or more critical objects in the at least one cell using the results of the linear programming solution.
摘要翻译：一种方法包括提取分级网格约束集合并将至少一个小区的一个或多个关键对象建模为变量集。该方法还包括基于具有变量集合的分级网格约束集来解决线性规划问题，以提供至少一个小区的关键对象的初始位置并且确定所述至少一个小区中的一个或多个关键对象的目标并网位置使用线性规划解决方案的结果的至少一个小区。

2. 发明申请

US20060101356A1 TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS 有权
标题翻译：用于具有放射性设计限制的集成电路的技术移动
公开(公告)号：US20060101356A1
公开(公告)日：2006-05-11
申请号：US10904225
申请日：2004-10-29
申请人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
发明人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。本发明实现了解决RDR要求的最小布局扰动方法。本发明还解决了在需要时插入虚拟形状的问题，并且延伸临界形状和/或虚拟形状的长度以满足“边缘覆盖”要求。

3. 发明申请

US20070198961A1 TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS 失效
标题翻译：用于具有放射性设计限制的集成电路的技术移动
公开(公告)号：US20070198961A1
公开(公告)日：2007-08-23
申请号：US11697798
申请日：2007-04-09
申请人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
发明人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. Also, a method, system and program product for migrating an integrated circuit design from a source technology without RDR to a target technology with RDR in which space may be reserved for late insertion of a feature and in which migration first occurs in a primary compaction direction having less tolerant ground rules.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。另外，一种用于将集成电路设计从没有RDR的源技术迁移到具有RDR的目标技术的方法，系统和程序产品，其中可以保留用于后期插入特征的空间，并且首先在初始压实方向上发生迁移具有较差的基本规则。

4. 发明申请

US20070277129A1 TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS 失效
标题翻译：用于具有放射性设计限制的集成电路的技术移动
公开(公告)号：US20070277129A1
公开(公告)日：2007-11-29
申请号：US11837732
申请日：2007-08-13
申请人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
发明人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。本发明实现了解决RDR要求的最小布局扰动方法。本发明还解决了在需要时插入虚拟形状的问题，并且延伸临界形状和/或虚拟形状的长度以满足“边缘覆盖”要求。

5. 发明申请

US20060101357A1 TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS 有权
标题翻译：用于具有放射性设计限制的集成电路的技术移动
公开(公告)号：US20060101357A1
公开(公告)日：2006-05-11
申请号：US10905008
申请日：2004-12-09
申请人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
发明人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. Also, a method, system and program product for migrating an integrated circuit design from a source technology without RDR to a target technology with RDR in which space may be reserved for late insertion of a feature and in which migration first occurs in a primary compaction direction having less tolerant ground rules.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。另外，一种用于将集成电路设计从没有RDR的源技术迁移到具有RDR的目标技术的方法，系统和程序产品，其中可以保留用于后期插入特征的空间，并且首先在初始压实方向上发生迁移具有较差的基本规则。

6. 发明申请

US20060085768A1 INTEGRATED CIRCUIT SELECTIVE SCALING 有权
标题翻译：集成电路选择性缩放
公开(公告)号：US20060085768A1
公开(公告)日：2006-04-20
申请号：US10711959
申请日：2004-10-15
申请人： Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Stephen Runyon , Robert Walker
发明人： Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Stephen Runyon , Robert Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Methods, systems and program products are disclosed for selectively scaling an integrated circuit (IC) design: by layer, by unit, or by ground rule, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield where new technologies such as maskless fabrication are implemented.
摘要翻译：公开了用于选择性地缩放集成电路（IC）设计的方法，系统和程序产品：按层，单元或基本规则，或这些的组合。在设计寿命期间，选择性缩放技术可以应用于具有过程和产量反馈的制造系统的反馈回路中，以便以保持层次结构的方式增加早期过程中的产量。本发明消除了在实现诸如无掩模制造之类的新技术的情况下使设计人员改进产量的需要。

7. 发明授权

US07454721B2 Method, apparatus and computer program product for optimizing an integrated circuit layout 失效
标题翻译：用于优化集成电路布局的方法，设备和计算机程序产品
公开(公告)号：US07454721B2
公开(公告)日：2008-11-18
申请号：US11276374
申请日：2006-02-27
申请人： Jason D. Hibbeler , Rani Narayan , Robert F. Walker
发明人： Jason D. Hibbeler , Rani Narayan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, apparatus, and computer program product for optimizing the layout of an integrated circuit design. Base ground rules and recommended ground rules are prioritized according to the impact they have on the yield of the integrated circuit design. The layout is optimized according to the prioritized base ground rules and recommended ground rules.
摘要翻译：一种用于优化集成电路设计布局的方法，装置和计算机程序产品。根据其对集成电路设计的收益的影响，将基础规则和建议的基本规则放在首位。布局根据优先的基础规则和推荐的基本规则进行优化。

8. 发明授权

US08627247B1 Systems and methods for fixing pin mismatch in layout migration 有权
标题翻译：在布局迁移中固定引脚不匹配的系统和方法
公开(公告)号：US08627247B1
公开(公告)日：2014-01-07
申请号：US13546562
申请日：2012-07-11
申请人： Kevin W. McCullen , Matthew T. Guzowski , Rani Narayan , Xiaoping Tang , Xin Yuan
发明人： Kevin W. McCullen , Matthew T. Guzowski , Rani Narayan , Xiaoping Tang , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Approaches are provided for fixing pin mismatches from swapping library cells in layout migration. Specifically, a method is provided that includes collecting information about a first technology pin from a library cell in a first technology. The method further includes swapping the library cell in the first technology with a library cell in a second technology. The method further includes collecting information about a second technology pin from the library cell in the second technology. The method further includes building a pin-mapping table that is configured to map the first technology pin to the second technology pin. The method further includes scaling a layout from the first technology to the second technology. The method further includes modifying the layout based on the pin-mapping table to match the at least one first technology pin to the at least one second technology pin while satisfying ground rules of the second technology.
摘要翻译：提供了用于在布局迁移中固定引脚不匹配的方法来交换库单元。具体地，提供了一种方法，其包括在第一技术中从库单元收集关于第一技术引脚的信息。该方法还包括在第二技术中用库单元交换第一技术中的库单元。该方法还包括在第二技术中从库单元收集关于第二技术引脚的信息。该方法还包括构建引脚映射表，其被配置为将第一技术引脚映射到第二技术引脚。该方法还包括将布局从第一技术缩放到第二技术。该方法还包括基于引脚映射表来修改布局，以在满足第二技术的基本规则的同时将至少一个第一技术引脚与至少一个第二技术引脚匹配。

9. 发明授权

US07257783B2 Technology migration for integrated circuits with radical design restrictions 有权
标题翻译：具有激进设计限制的集成电路的技术迁移
公开(公告)号：US07257783B2
公开(公告)日：2007-08-14
申请号：US10905008
申请日：2004-12-09
申请人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
发明人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. Also, a method, system and program product for migrating an integrated circuit design from a source technology without RDR to a target technology with RDR in which space may be reserved for late insertion of a feature and in which migration first occurs in a primary compaction direction having less tolerant ground rules.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。另外，一种用于将集成电路设计从没有RDR的源技术迁移到具有RDR的目标技术的方法，系统和程序产品，其中可以保留用于后期插入特征的空间，并且首先在初始压实方向上发生迁移具有较差的基本规则。

10. 发明申请

US20120233576A1 SCHEMATIC-BASED LAYOUT MIGRATION 审中-公开
标题翻译：基于模式的布局迁移
公开(公告)号：US20120233576A1
公开(公告)日：2012-09-13
申请号：US13043761
申请日：2011-03-09
申请人： Geoffrey R. Barrows , Derick G. Behrends , William J. Craig , Michael S. Gray , Matthew T. Guzowski , Kevin W. McCullen , Rani Narayan , Robert F. Walker
发明人： Geoffrey R. Barrows , Derick G. Behrends , William J. Craig , Michael S. Gray , Matthew T. Guzowski , Kevin W. McCullen , Rani Narayan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Method, system, computer, etc., embodiments receive an original integrated circuit design into a computerized device. The methods herein automatically replace at least some of the original cells within the original integrated circuit design with replacement cells using the computerized device. Each of the replacement cells has an initial cell size that is unassociated with any specific design size. The methods herein automatically change the original design size of the integrated circuit design to a changed design size, and automatically individually change the initial cell size of each of the replacement cells to different sizes. At least two different replacement cells are changed from the initial cell size by different size reduction amounts based on different amounts of space required within the changed design size for each of the replacement cells.
摘要翻译：方法，系统，计算机等实施例将原始集成电路设计接收到计算机化设备中。本文中的方法使用计算机化设备自动地用原始集成电路设计中的至少一些原始单元替换替换单元。每个替换单元格具有与任何特定设计尺寸无关的初始单元格大小。这里的方法将集成电路设计的原始设计尺寸自动地改变为改变的设计尺寸，并且将每个替换单元的初始单元尺寸自动地单独地改变为不同的尺寸。基于每个替换单元的改变的设计尺寸中所需的不同的空间量，将至少两个不同的替换单元从初始单元大小改变为不同的尺寸减小量。

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