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1. 发明授权

US08575972B2 Digital frequency synthesizer device and method thereof 有权
标题翻译：数字频率合成器装置及其方法
公开(公告)号：US08575972B2
公开(公告)日：2013-11-05
申请号：US12409228
申请日：2009-03-23
申请人： Richard W. Reeves , Spencer M. Gold , Steven J. Kommrusch , Anwar P. Kashem
发明人： Richard W. Reeves , Spencer M. Gold , Steven J. Kommrusch , Anwar P. Kashem
IPC分类号： H03B21/00 , H03K3/00
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/324 , Y02D10/126
摘要： A first plurality of clock signals including a first clock signal and a second clock signal is received, the first and second clock signal out of phase with each other. A second plurality of clock signals comprising a third clock signal and a fourth clock signal is received, the third and fourth clock signals out of phase with each other. A plurality of enable signals are received. A fifth clock signal is determined based on the first plurality of clock signals and the plurality of enable signals. A sixth clock signal is determined based on the second plurality of clock signals and the plurality of enable signals. A seventh clock signal is determined based on the fifth clock signal and the sixth clock signal.
摘要翻译：接收包括第一时钟信号和第二时钟信号的第一多个时钟信号，第一和第二时钟信号彼此异相。接收包括第三时钟信号和第四时钟信号的第二多个时钟信号，第三和第四时钟信号彼此不同相。接收多个使能信号。基于第一多个时钟信号和多个使能信号来确定第五时钟信号。基于第二多个时钟信号和多个使能信号来确定第六时钟信号。基于第五时钟信号和第六时钟信号确定第七时钟信号。

2. 发明申请

US20100237924A1 DIGITAL FREQUENCY SYNTHESIZER DEVICE AND METHOD THEREOF 有权
标题翻译：数字频率合成器件及其方法
公开(公告)号：US20100237924A1
公开(公告)日：2010-09-23
申请号：US12409228
申请日：2009-03-23
申请人： Richard W. Reeves , Spencer M. Gold , Steven J. Kommrusch , Anwar P. Kashem
发明人： Richard W. Reeves , Spencer M. Gold , Steven J. Kommrusch , Anwar P. Kashem
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/324 , Y02D10/126
摘要： A first plurality of clock signals including a first clock signal and a second clock signal is received, the first and second clock signal out of phase with each other. A second plurality of clock signals comprising a third clock signal and a fourth clock signal is received, the third and fourth clock signals out of phase with each other. A plurality of enable signals are received. A fifth clock signal is determined based on the first plurality of clock signals and the plurality of enable signals. A sixth clock signal is determined based on the second plurality of clock signals and the plurality of enable signals. A seventh clock signal is determined based on the fifth clock signal and the sixth clock signal.
摘要翻译：接收包括第一时钟信号和第二时钟信号的第一多个时钟信号，第一和第二时钟信号彼此异相。接收包括第三时钟信号和第四时钟信号的第二多个时钟信号，第三和第四时钟信号彼此不同相。接收多个使能信号。基于第一多个时钟信号和多个使能信号来确定第五时钟信号。基于第二多个时钟信号和多个使能信号来确定第六时钟信号。基于第五时钟信号和第六时钟信号确定第七时钟信号。

3. 发明授权

US07007188B1 Precision bypass clock for high speed testing of a data processor 失效
标题翻译：精密旁路时钟，用于数据处理器的高速测试
公开(公告)号：US07007188B1
公开(公告)日：2006-02-28
申请号：US10426049
申请日：2003-04-29
申请人： Brett A. Tischler , Steven J. Kommrusch
发明人： Brett A. Tischler , Steven J. Kommrusch
IPC分类号： G06F1/04
CPC分类号： G06F1/08
摘要： A system clock circuit that provides a high-speed reference clock signal for operating an integrated circuit. The system clock circuit comprises a frequency combiner circuit that receives a first external clock signal having a frequency F1 and a second external clock signal having frequency F2, where F2 is an integer multiple of F1. The second external clock signal is phase-shifted by P degrees with respect to the first external clock signal. The frequency combiner circuit generates from the first and second external clock signals a first output clock signal having an operating frequency that is the sum of F1 and F2. The system clock circuit also comprises a clock selection circuit that selectively applies the first output clock signal to the integrated circuit.
摘要翻译：一种提供用于操作集成电路的高速参考时钟信号的系统时钟电路。系统时钟电路包括接收具有频率F1的第一外部时钟信号和具有频率F2的第二外部时钟信号的频率合成器电路，其中F2是F1的整数倍。第二外部时钟信号相对于第一外部时钟信号相移P度。频率合成器电路从第一和第二外部时钟信号产生具有作为F1和F2之和的工作频率的第一输出时钟信号。系统时钟电路还包括选择性地将第一输出时钟信号施加到集成电路的时钟选择电路。

4. 发明授权

US5444838A Computer system and method for interference checking of polyhedra using capping polygons 失效
标题翻译：使用封盖多边形进行多面体干涉检查的计算机系统和方法
公开(公告)号：US5444838A
公开(公告)日：1995-08-22
申请号：US671070
申请日：1991-03-18
申请人： Steven J. Kommrusch , Daniel G. Schmidt , Howard D. Stroyan
发明人： Steven J. Kommrusch , Daniel G. Schmidt , Howard D. Stroyan
IPC分类号： G06T17/00 , G06T17/40
CPC分类号： G06T17/00
摘要： A computer graphics system configured to allow a user to move at least one sectioning plane about at least one polyhedron having a plurality of polygons and to display, if necessary, an interference area between the plurality of polygons is disclosed. The computer graphics system first comprises at least one processor and at least one memory unit configured with the computer graphics system to process data. The computer graphics system further comprises an input device configured with the computer graphics system to allow the user to specify the at least one sectioning plane. The computer graphics system further comprises an interference checking module configured with the computer graphics system to generate an interference cap polygon indicative of the interference area. The computer graphics system further comprises a display device configured with the computer graphics system to display the interference cap polygon.
摘要翻译：一种计算机图形系统，被配置为允许用户围绕具有多个多边形的至少一个多面体移动至少一个分段平面，并且如有必要，显示多个多边形之间的干涉区域。计算机图形系统首先包括至少一个处理器和配置有计算机图形系统以处理数据的至少一个存储器单元。计算机图形系统还包括配置有计算机图形系统的输入设备，以允许用户指定至少一个分段平面。所述计算机图形系统还包括配置有所述计算机图形系统以产生指示所述干扰区域的干扰帽多边形的干扰检查模块。计算机图形系统还包括配置有计算机图形系统以显示干涉帽多边形的显示装置。

5. 发明授权

US08584067B2 Clock domain crossing buffer 有权
标题翻译：时钟域交叉缓冲区
公开(公告)号：US08584067B2
公开(公告)日：2013-11-12
申请号：US12938125
申请日：2010-11-02
申请人： Michael J. Osborn , Michael J. Tresidder , Aaron J. Grenat , Joseph Kidd , Priyank Parakh , Steven J. Kommrusch
发明人： Michael J. Osborn , Michael J. Tresidder , Aaron J. Grenat , Joseph Kidd , Priyank Parakh , Steven J. Kommrusch
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： H03K5/153 , G06F17/5009 , G06F17/5031 , G06F2217/84
摘要： Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.
摘要翻译：公开了关于检测和最小化由集成电路中的时钟域交叉（CDC）产生的定时问题的技术。在各种实施例中，一个或多个定时参数与集成电路中的时钟域之间的路径相关联，其中一个或多个定时参数指定路径的传播延迟。在一个实施例中，定时参数可以使用配置文件分发到不同的设计阶段。在一些实施例中，一个或多个参数可以与RTL模型一起使用以模拟沿着路径的数据信号的传播。在一些实施例中，一个或多个参数可以与网表结合使用，以便为集成电路创建物理设计，其中物理设计包括具有指定的传播延迟的路径的表示。

6. 发明申请

US20120144240A1 DEBUG STATE MACHINE AND PROCESSOR INCLUDING THE SAME 有权
标题翻译：调试状态机和处理器，包括它们
公开(公告)号：US20120144240A1
公开(公告)日：2012-06-07
申请号：US12958585
申请日：2010-12-02
申请人： Eric Rentschler , Steven J. Kommrusch , Scott P. Nixon
发明人： Eric Rentschler , Steven J. Kommrusch , Scott P. Nixon
IPC分类号： G06F11/07
CPC分类号： G06F11/3636
摘要： A processor or an integrated circuit chip including a debug state machine (DSM) that allows for programming complex triggering sequences for flexible and efficient debug visibility is disclosed. The DSM centralizes control of local debug functions such as trace start and stop, trace filtering, cross triggering between DSMs, clock stopping, triggering a system debug mode interrupt, flexible microcode interface, and the like. The DSM is configured to receive triggers from a processor core, other DSMs, a northbridge, other sockets, and the like and initiate a programmed action on a condition that a corresponding trigger or a sequence of triggers occurs.
摘要翻译：公开了一种处理器或集成电路芯片，其包括调试状态机（DSM），其允许编程复杂的触发序列以实现灵活和有效的调试可见性。 DSM集中控制本地调试功能，如跟踪启动和停止，跟踪过滤，DSM之间的交叉触发，时钟停止，触发系统调试模式中断，灵活的微代码接口等。 DSM被配置为从处理器核心，其他DSM，北桥，其他插座等接收触发，并且在相应的触发或触发序列发生的条件下启动编程的动作。

7. 发明授权

US07426621B2 Memory access request arbitration 有权
标题翻译：内存访问请求仲裁
公开(公告)号：US07426621B2
公开(公告)日：2008-09-16
申请号：US11297856
申请日：2005-12-09
申请人： Steven J. Kommrusch , Brett A. Tischler
发明人： Steven J. Kommrusch , Brett A. Tischler
IPC分类号： G06F13/28
CPC分类号： G06F13/1631
摘要： A method includes receiving a first memory access request from a first device during a first interval. The first memory access request is to access a first page of a multiple-page memory. The method further includes receiving a second memory access request from the first device during a second interval subsequent to the first interval and receiving a third memory access request from a second device during the second interval. The method additionally includes preferentially selecting the second memory access request over the third memory access request for provision to the multiple-page memory if an indicator indicates the second memory access request is expected to access the first page of the multiple-page memory.
摘要翻译：一种方法包括在第一间隔期间从第一设备接收第一存储器访问请求。第一个存储器访问请求是访问多页存储器的第一页。该方法还包括在第一间隔之后的第二间隔期间从第一设备接收第二存储器访问请求，并且在第二间隔期间从第二设备接收第三存储器访问请求。该方法还包括：如果指示符指示第二存储器访问请求预期访问多页存储器的第一页，则优先地通过第三存储器访问请求选择第二存储器访问请求以提供给多页存储器。

8. 发明授权

US06424691B1 Phase locked loop clock divider utilizing a high speed programmable linear feedback shift register 有权
标题翻译：锁相环时钟分频器利用高速可编程线性反馈移位寄存器
公开(公告)号：US06424691B1
公开(公告)日：2002-07-23
申请号：US09960590
申请日：2001-09-21
申请人： Karthik R. Neravetla , Steven J. Kommrusch
发明人： Karthik R. Neravetla , Steven J. Kommrusch
IPC分类号： H03K2100
CPC分类号： H03K23/54 , H03K23/665
摘要： An apparatus and method is disclosed for providing a phase locked loop clock divider circuit utilizing a high speed linear feedback shift register. A plurality of pre-load flip flop (PLFF) circuits and multiplexers are coupled to a plurality of linear feedback shift register (LFSR) flip flop units and multiplexers. The PLFF circuits hold two initial LFSR sequence values. A load enable signal to the PLFF multiplexers and LFSR multiplexers is high for two input clock cycles. The present invention is capable of operating at high frequencies due to a shortened critical timing path.
摘要翻译：公开了一种用于提供利用高速线性反馈移位寄存器的锁相环时钟分频器电路的装置和方法。多个预加载触发器（PLFF）电路和多路复用器耦合到多个线性反馈移位寄存器（LFSR）触发器单元和多路复用器。 PLFF电路保持两个初始LFSR序列值。对于两个输入时钟周期，到PLFF多路复用器和LFSR复用器的加载使能信号为高电平。由于临时定时路径的缩短，本发明能够在高频下工作。

9. 发明授权

US5446496A Frame rate conversion with asynchronous pixel clocks 失效
标题翻译：具有异步像素时钟的帧速率转换
公开(公告)号：US5446496A
公开(公告)日：1995-08-29
申请号：US221433
申请日：1994-03-31
申请人： Bradly J. Foster , David J. Hodge , Steven J. Kommrusch
发明人： Bradly J. Foster , David J. Hodge , Steven J. Kommrusch
IPC分类号： H04N5/04 , G09G3/20 , G09G5/00 , G09G5/39 , H04N7/01 , H04N9/64
CPC分类号： G09G5/005 , G09G5/39 , H04N7/01 , H04N7/0105 , G09G2340/0435 , G09G2360/18 , G09G5/006
摘要： A frame rate conversion system synchronizes data transfers to and from a VRAM frame buffer which are concurrent, continuous, and asynchronous. The system comprises a frame buffer having a split memory for communicating data to a split output shift register. A frame buffer control supervises writing operations to the split memory at a first frame rate. A display control supervises reading operations from the shift register at a second frame rate which is slower than the first frame rate. The frame buffer control and the display control communicate control signals through double synchronizers. The display control has a counter for counting frames of data which have been read from the VRAM frame buffer. The display control prevents the writing of a frame into the split memory after a particular number of frames has been counted so as to prevent the frame buffer control from writing over and destroying existing data which has not yet been read from the split memory by the display control. Moreover, the display control synchronizes the writing and reading operations by the frame buffer control and the display control, respectively, each time that a frame has been skipped. Furthermore, the frame buffer control causes the VRAM frame buffer to transfer data from the split memory to the shift register when the horizontal blank is deasserted within the incoming analog video signal.
摘要翻译：帧速率转换系统将数据传输与来自并发，连续和异步的VRAM帧缓冲器进行同步。该系统包括具有用于将数据传送到分离输出移位寄存器的分离存储器的帧缓冲器。帧缓冲器控制以第一帧速率监视对分离存储器的写入操作。显示控制器以比第一帧速率慢的第二帧速率监视来自移位寄存器的读取操作。帧缓冲器控制和显示控制通过双同步器传送控制信号。显示控制具有用于计数从VRAM帧缓冲器读取的数据帧的计数器。显示控制防止在特定数量的帧被计数之后将帧写入分离存储器，以防止帧缓冲器控制通过显示器写入并破坏尚未从分离存储器读取的现有数据控制。此外，每当帧被跳过时，显示控制分别通过帧缓冲器控制和显示控制来同步写入和读取操作。此外，当输入模拟视频信号中的空白被取消置位时，帧缓冲器控制使得VRAM帧缓冲器将数据从分离存储器传送到移位寄存器。

10. 发明授权

US09037911B2 Debug state machines and methods of their operation 有权
标题翻译：调试状态机及其操作方法
公开(公告)号：US09037911B2
公开(公告)日：2015-05-19
申请号：US13095627
申请日：2011-04-27
申请人： Eric M. Rentschler , Steven J. Kommrusch , Scott Nixon
发明人： Eric M. Rentschler , Steven J. Kommrusch , Scott Nixon
IPC分类号： G06F11/00 , G06F11/267 , G06F11/22
CPC分类号： G06F11/267 , G06F11/22
摘要： Embodiments include methods for performing various operations in a computing system that includes an electronic module and a debug circuit. The method includes programming the debug circuit to monitor for pre-selected triggers produced by the computing system, and to perform actions in response to detecting the pre-select triggers. For example, in response to various pre-selected triggers, the debug circuit may, among other things: perform state transitions and log information indicating whether or not the state transitions were performed; monitor various signals when the debug circuit has determined that a test escape has occurred; and/or perform one or more actions that initiate stopping one or more clocks in response to certain pre-selected triggers.
摘要翻译：实施例包括用于在包括电子模块和调试电路的计算系统中执行各种操作的方法。该方法包括对调试电路进行编程以监视由计算系统产生的预先选择的触发，并且响应于检测到预选触发而执行动作。例如，响应于各种预先选择的触发，调试电路可以除其他之外：执行状态转换和指示状态转换是否被执行的日志信息; 当调试电路确定已经发生测试逃生时，监视各种信号; 和/或执行响应于某些预先选择的触发而启动停止一个或多个时钟的一个或多个动作。

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