专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06252270B1 Increased cycle specification for floating-gate and method of manufacture thereof 失效
标题翻译：增加浮栅的循环规范及其制造方法
公开(公告)号：US06252270B1
公开(公告)日：2001-06-26
申请号：US08848114
申请日：1997-04-28
申请人： Richard W. Gregor , Isik C. Kizilyalli , Ranbir Singh
发明人： Richard W. Gregor , Isik C. Kizilyalli , Ranbir Singh
IPC分类号： H01L29788
CPC分类号： H01L21/28194 , H01L29/42324 , H01L29/4916 , H01L29/51 , H01L29/513 , H01L29/7883 , H01L29/7886
摘要： A programmable semiconductor device and a method of manufacturing the same. The device includes: (1) a substrate composed at least in part of silicon, (2) a dielectric layer located over the substrate and (3) a control gate located over the dielectric layer wherein the dielectric layer contains a substantial concentration of an isotope of hydrogen.
摘要翻译：一种可编程半导体器件及其制造方法。该装置包括：（1）至少部分由硅组成的衬底，（2）位于衬底上的电介质层和（3）位于电介质层上方的控制栅极，其中介电层含有相当浓度的同位素的氢。

2. 发明授权

US6023093A Deuterated direlectric and polysilicon film-based semiconductor devices and method of manufacture thereof 失效
标题翻译：氘代电介质和多晶硅薄膜半导体器件及其制造方法
公开(公告)号：US6023093A
公开(公告)日：2000-02-08
申请号：US847704
申请日：1997-04-28
申请人： Richard W. Gregor , Isik C. Kizilyalli
发明人： Richard W. Gregor , Isik C. Kizilyalli
IPC分类号： H01L21/8247 , H01L21/205 , H01L21/30 , H01L21/336 , H01L21/762 , H01L21/8238 , H01L27/10 , H01L27/115 , H01L29/49 , H01L29/78 , H01L29/788 , H01L29/792 , H01L23/58
CPC分类号： H01L29/6659 , H01L21/3003 , H01L21/76213 , H01L21/823857 , H01L21/823864 , H01L21/823878 , H01L29/4983
摘要： A semiconductor device and a method of manufacturing the semiconductor device. The device includes: (1) a substrate composed at least in part of silicon and (2) a film located over the substrate and having a substantial concentration of an isotope of hydrogen located in the film.
摘要翻译：一种半导体器件及其制造方法。该装置包括：（1）至少部分由硅构成的衬底和（2）位于衬底上的膜，并且具有位于膜中的氢的同位素的相当浓度。

3. 发明授权

US06359339B1 Multi-layered metal silicide resistor for Si Ic's 有权
标题翻译： Si Ic的多层金属硅化物电阻
公开(公告)号：US06359339B1
公开(公告)日：2002-03-19
申请号：US09480224
申请日：2000-01-10
申请人： Richard W. Gregor , Isik C. Kizilyalli , Sailesh M. Merchant , Jaseph R. Radosevich , Pradip K. Roy
发明人： Richard W. Gregor , Isik C. Kizilyalli , Sailesh M. Merchant , Jaseph R. Radosevich , Pradip K. Roy
IPC分类号： H01L2348
CPC分类号： H01L28/24 , H01L27/0802
摘要： The present invention provides a unique a resistor formed on a semiconductor substrate. The resistor preferably comprises a first resistor layer that includes a first metal silicide, such as tungsten silicide, and nitrogen and that is formed on the substrate. The first layer has a first thickness and a concentration of nitrogen incorporated therein. The nitrogen concentration may be varied to obtain a desired resistive value of the resistor. Thus, depending on the concentration of nitrogen, a wide range of resistive values may be achieved. The resistor further comprises a second resistor layer with a second thickness that includes a second metal silicide and that is formed on the first resistor layer. Thus, the present invention provides a metal silicide-based resistor having nitrogen incorporated therein which allows the resistance of the resistor to be tailored to specific electrical applications. Yet at the same time, the resistor is far less susceptible to temperature and voltage variation than conventional diffused resistors and, thereby, provides a more precise resistor.
摘要翻译：本发明提供了形成在半导体衬底上的独特的电阻器。电阻器优选地包括第一电阻层，该第一电阻层包括第一金属硅化物，例如硅化钨和氮，并且形成在衬底上。第一层具有掺入其中的第一厚度和氮浓度。可以改变氮浓度以获得电阻器的期望电阻值。因此，取决于氮的浓度，可以实现宽范围的电阻值。电阻器还包括具有第二厚度的第二电阻层，该第二电阻层包括第二金属硅化物，并形成在第一电阻层上。因此，本发明提供一种其中结合有氮化物的金属硅化物基电阻器，其允许将电阻器的电阻定制为特定的电气应用。然而与此同时，电阻器比常规扩散电阻器更不易受温度和电压变化的影响，从而提供更精确的电阻器。

4. 发明授权

US06680542B1 Damascene structure having a metal-oxide-metal capacitor associated therewith 有权
标题翻译：具有与其相关联的金属氧化物 - 金属电容器的镶嵌结构
公开(公告)号：US06680542B1
公开(公告)日：2004-01-20
申请号：US09575214
申请日：2000-05-18
申请人： Gerald W. Gibson , Richard W. Gregor , Chun-Yung Sung , Daniel J. Vitkavage , Allen Yen
发明人： Gerald W. Gibson , Richard W. Gregor , Chun-Yung Sung , Daniel J. Vitkavage , Allen Yen
IPC分类号： H01L2348
CPC分类号： H01L28/40 , H01L23/5223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device, including an interconnect and a capacitor, and a method of fabrication therefor. The method includes forming a damascene interconnect structure through an interlevel dielectric layer and a dielectric etch stop layer located under the interlevel dielectric, wherein the damascene interconnect structure contacts a first interconnect structure. The method further includes forming a metal-oxide-metal (MOM) capacitor damascene structure through the interlevel dielectric layer and terminating on the dielectric etch stop layer. The damascene structures, may in an alternative embodiment, be dual damascene structures. Furthermore, the damascene interconnect structure and the MOM capacitor may, in another embodiment, make up part of a larger integrated circuit.
摘要翻译：本发明提供一种包括互连和电容器的半导体器件及其制造方法。该方法包括通过层间电介质层和位于层间电介质下面的电介质蚀刻停止层形成镶嵌互连结构，其中镶嵌互连结构接触第一互连结构。该方法还包括通过层间电介质层形成金属氧化物金属（MOM）电容器镶嵌结构，并终止在介电蚀刻停止层上。在替代实施例中，镶嵌结构可以是双镶嵌结构。此外，在另一个实施例中，镶嵌互连结构和MOM电容器可以构成较大集成电路的一部分。

5. 发明授权

US5312781A Flash EEPROM fabrication process that uses a selective wet chemical etch 失效
标题翻译：闪存EEPROM制造工艺，使用选择性湿化学蚀刻
公开(公告)号：US5312781A
公开(公告)日：1994-05-17
申请号：US792496
申请日：1991-11-12
申请人： Richard W. Gregor , Chung W. Leung
发明人： Richard W. Gregor , Chung W. Leung
IPC分类号： H01L21/311 , H01L21/00 , H01L21/02 , H01L21/302 , H01L21/463
CPC分类号： H01L21/31111 , Y10S438/978
摘要： A method for wet etching disposable spacers in silicon integrated circuits is provided. Illustratively, a pair of spacers is formed over a polysilicon substrate. A second pair of spacers is formed from doped silicon dioxide over the first pair of spacers. Then the second pair of spacers is etched away with NH.sub.4 OH/H.sub.2 O.sub.2, thus providing a means for defining the underlying polysilicon layer, e.g., by etching.
摘要翻译：提供了一种用于湿式蚀刻硅集成电路中的一次性间隔物的方法。说明性地，在多晶硅衬底上形成一对衬垫。第二对间隔物由第一对间隔物上的掺杂二氧化硅形成。然后用NH 4 OH / H 2 O 2蚀刻掉第二对间隔物，从而提供了例如通过蚀刻来定义下面的多晶硅层的手段。

6. 发明授权

US5110756A Method of semiconductor integrated circuit manufacturing which includes processing for reducing defect density 失效
标题翻译：包括减少缺陷密度的处理的半导体集成电路制造方法
公开(公告)号：US5110756A
公开(公告)日：1992-05-05
申请号：US725706
申请日：1991-07-03
申请人： Richard W. Gregor , Chung W. Leung
发明人： Richard W. Gregor , Chung W. Leung
IPC分类号： H01L21/322 , H01L21/32 , H01L21/762
CPC分类号： H01L21/32 , H01L21/76221
摘要： Defect density in a semiconductor process sequence that uses two local oxidations is reduced by using an approximately 1:1 ratio of nitride to oxide thickness in the second local oxidation step and an annealing step.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式