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1. 发明授权

US5312781A Flash EEPROM fabrication process that uses a selective wet chemical etch 失效
标题翻译：闪存EEPROM制造工艺，使用选择性湿化学蚀刻
公开(公告)号：US5312781A
公开(公告)日：1994-05-17
申请号：US792496
申请日：1991-11-12
申请人： Richard W. Gregor , Chung W. Leung
发明人： Richard W. Gregor , Chung W. Leung
IPC分类号： H01L21/311 , H01L21/00 , H01L21/02 , H01L21/302 , H01L21/463
CPC分类号： H01L21/31111 , Y10S438/978
摘要： A method for wet etching disposable spacers in silicon integrated circuits is provided. Illustratively, a pair of spacers is formed over a polysilicon substrate. A second pair of spacers is formed from doped silicon dioxide over the first pair of spacers. Then the second pair of spacers is etched away with NH.sub.4 OH/H.sub.2 O.sub.2, thus providing a means for defining the underlying polysilicon layer, e.g., by etching.
摘要翻译：提供了一种用于湿式蚀刻硅集成电路中的一次性间隔物的方法。说明性地，在多晶硅衬底上形成一对衬垫。第二对间隔物由第一对间隔物上的掺杂二氧化硅形成。然后用NH 4 OH / H 2 O 2蚀刻掉第二对间隔物，从而提供了例如通过蚀刻来定义下面的多晶硅层的手段。

2. 发明授权

US5110756A Method of semiconductor integrated circuit manufacturing which includes processing for reducing defect density 失效
标题翻译：包括减少缺陷密度的处理的半导体集成电路制造方法
公开(公告)号：US5110756A
公开(公告)日：1992-05-05
申请号：US725706
申请日：1991-07-03
申请人： Richard W. Gregor , Chung W. Leung
发明人： Richard W. Gregor , Chung W. Leung
IPC分类号： H01L21/322 , H01L21/32 , H01L21/762
CPC分类号： H01L21/32 , H01L21/76221
摘要： Defect density in a semiconductor process sequence that uses two local oxidations is reduced by using an approximately 1:1 ratio of nitride to oxide thickness in the second local oxidation step and an annealing step.

3. 发明授权

US06191980B1 Single-poly non-volatile memory cell having low-capacitance erase gate 有权
标题翻译：具有低电容擦除栅极的单多晶非易失性存储单元
公开(公告)号：US06191980B1
公开(公告)日：2001-02-20
申请号：US09583505
申请日：2000-05-31
申请人： Patrick J. Kelley , Ross A. Kohler , Chung W. Leung , Richard J. McPartland , Ranbir Singh
发明人： Patrick J. Kelley , Ross A. Kohler , Chung W. Leung , Richard J. McPartland , Ranbir Singh
IPC分类号： G11C1604
CPC分类号： G11C16/0408 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A single-poly flash memory cell has a control device, a switch device, and an erase device, all of which share a common polysilicon floating gate which is designed to retain charge in the programmed memory cell. The memory cell is erased by applying an erase voltage to the tub of the erase device to cause tunneling across the oxide layer separating the floating gate from the rest of the erase device structure. Since a typical tub-to-source/drain breakdown voltage (e.g., 15 volts) is greater than a typical erase voltage (e.g., 10 volts), the memory cell can be safely erased without risking the junction breakdowns that are associated with other prior art single-poly memory cell designs for deep sub-micron technologies (e.g., 0.25-micron and lower).
摘要翻译：单聚焦闪存单元具有控制装置，开关装置和擦除装置，所有这些都共享共同的多晶硅浮动栅极，其被设计为在编程的存储器单元中保持电荷。通过向擦除装置的桶施加擦除电压来擦除存储器单元，以使隔离浮动栅极与擦除装置结构的其余部分的氧化物层的隧穿。由于典型的桶到源极/漏极击穿电压（例如15伏特）大于典型的擦除电压（例如，10伏特），所以可以安全地擦除存储器单元，而不会与与其它先前相关联的结点故障用于深亚微米技术（例如，0.25微米及更低）的单一多晶硅记忆体设计。

4. 发明授权

US5102827A Contact metallization of semiconductor integrated-circuit devices 失效
标题翻译：接触半导体集成电路器件的金属化
公开(公告)号：US5102827A
公开(公告)日：1992-04-07
申请号：US732947
申请日：1991-07-19
申请人： Min-Liang Chen , Chung W. Leung
发明人： Min-Liang Chen , Chung W. Leung
IPC分类号： H01L21/285 , H01L21/768 , H01L23/532
CPC分类号： H01L23/53223 , H01L21/28518 , H01L21/76838 , H01L2924/0002
摘要： In the manufacture of semiconductor integrated-circuit devices, electrical contact to semiconductor regions such as, e.g., source and drain regions of field-effect transistors typically is made by a structure in which a silicide is intermediary to silicon and metal. The invention provides for processing, after window formation and before metal deposition, which includes deposition of a silicide-forming material, and annealing in a non-oxidizing atmosphere. Preferably, the atmosphere includes a component which forms a conductive compound with the silicide-forming material. Resulting contact structures have good step coverage, low contact resistance, low interdiffusion of metal into semiconductor, and fail-safe operation in the event of breaks due to electromigration. Moreover, in the case of misalignment of a window, a contact region may be extended laterally by dopant diffusion, thereby safeguarding the junction. Tolerance to window misalignment permits increased packing density, e.g., in dynamic random-access memory arrays.
摘要翻译：在半导体集成电路器件的制造中，与半导体区域（例如场效应晶体管的源区和漏极区）的电接触通常由其中硅化物介于硅和金属之间的结构制成。本发明提供了窗口形成之后和金属沉积之前的处理，其包括沉积硅化物形成材料，以及在非氧化性气氛中进行退火。优选地，气氛包括与硅化物形成材料形成导电化合物的组分。导致的接触结构具有良好的台阶覆盖率，低接触电阻，金属到半导体的低相互扩散性，以及由于电迁移而导致断路的故障安全操作。此外，在窗口未对准的情况下，可以通过掺杂剂扩散横向延伸接触区域，从而保护接合部。对窗口偏移的容限允许增加打包密度，例如在动态随机存取存储器阵列中。

5. 发明授权

US4886765A Method of making silicides by heating in oxygen to remove contamination 失效
标题翻译：通过在氧气中加热以除去污染物来制造硅化物的方法
公开(公告)号：US4886765A
公开(公告)日：1989-12-12
申请号：US262773
申请日：1988-10-26
申请人： Min-Liang Chen , Chung W. Leung , Chih-Yuan Lu , Nun-Sian Tsai
发明人： Min-Liang Chen , Chung W. Leung , Chih-Yuan Lu , Nun-Sian Tsai
IPC分类号： H01L21/28 , H01L21/3105
CPC分类号： H01L21/3105 , H01L21/28052 , Y10S148/017 , Y10S148/019 , Y10S438/906 , Y10S438/909
摘要： Silicides are important for submicron VLSIC technology. Problems have been found in forming silicides by known techniques involving simply depositing a metal film and heating that metal to form a silicide layer. This invention solves the problems through recognition that polymeric contamination can be left on the surface from commonly-used previous reactive ion etch steps, and removes any such contamination to metal deposition by the additional step of heating in dry oxygen at a low temperature, such as 800 degrees Centigrade, before the contamination has been significantly hardened.
摘要翻译：硅胶对亚微米VLSIC技术很重要。在通过简单地沉积金属膜并加热该金属以形成硅化物层的已知技术来形成硅化物中已经发现了问题。本发明解决了这些问题，通过识别聚合物污染物可以从通常使用的先前的反应离子蚀刻步骤留在表面上，并且通过在低温下在干燥氧气中加热的附加步骤来除去金属沉积物中的任何这样的污染物，例如 800摄氏度之前，污染已经显着硬化。

6. 发明授权

US5045898A CMOS integrated circuit having improved isolation 失效
标题翻译： CMOS集成电路具有改进的隔离
公开(公告)号：US5045898A
公开(公告)日：1991-09-03
申请号：US238362
申请日：1988-08-30
申请人： Min-Liang Chen , William T. Cochran , Chung W. Leung
发明人： Min-Liang Chen , William T. Cochran , Chung W. Leung
IPC分类号： H01L21/762 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/823878 , H01L21/76218 , H01L27/0928
摘要： A p-type tub in a CMOS integrated circuit is isolated from the adjacent n-type tub by means of a field oxide having a p-type channel stop region formed by a boron ion implant. The depth of the ion implant is selected so that the peak of the boron concentration is located immediately under the field oxide region that is subsequently grown. In addition, the implant is allowed to penetrate into the active device regions, producing a retrograde boron concentration in the n-channel region. This technique simultaneously improves device isolation and n-channel transistor punch-through characteristics, allowing the extension of CMOS technology to sub-micron device geometries.

7. 发明授权

US4420503A Low temperature elevated pressure glass flow/re-flow process 失效
标题翻译：低温高压玻璃流/再流程
公开(公告)号：US4420503A
公开(公告)日：1983-12-13
申请号：US379103
申请日：1982-05-17
申请人： Chung W. Leung , Robert H. Dawson , Martin A. Blumenfeld , Dennis P. Biondi
发明人： Chung W. Leung , Robert H. Dawson , Martin A. Blumenfeld , Dennis P. Biondi
IPC分类号： H01L21/3105 , H01L21/316
CPC分类号： H01L21/3105 , Y10S438/978
摘要： A method of reducing the time and temperature for either flowing or re-flowing a glass layer on a semiconductor device is described. The method involves conducting the flow or re-flow process steps at an elevated pressure which reduces both the time and the temperature required to achieve proper flow and re-flow characteristics.
摘要翻译：描述了一种减少在半导体器件上流动或再流动玻璃层的时间和温度的方法。该方法包括在升高的压力下进行流动或再流动过程步骤，这降低了实现适当流动和再流动特性所需的时间和温度。

8. 发明授权

US4905073A Integrated circuit with improved tub tie 失效
标题翻译：集成电路与改进的领带
公开(公告)号：US4905073A
公开(公告)日：1990-02-27
申请号：US376919
申请日：1989-07-03
申请人： Min-Liang Chen , Chung W. Leung , Daniel M. Wroge
发明人： Min-Liang Chen , Chung W. Leung , Daniel M. Wroge
IPC分类号： H01L21/8238 , H01L23/485 , H01L27/092
CPC分类号： H01L21/823814 , H01L23/485 , H01L27/0928 , H01L2924/0002
摘要： When making CMOS logic circuits, for example an inverter, it is frequently necessary to connect the sources of the p and n channel transistors to their respective tubs (n and p, respectively). The prior art required either a large contact window covering both source and tub regions, or else two standard size contact windows. The present technique forms the tub tie connection by the use of the same silicide layer that is formed on the source/drain regions, which typically also forms a gate silicide in the self-aligned silicide (i.e., "salicide") process. A conventional window may then be used to connect the silicide tub tie (and hence the source/tub regions) to a power supply conductor. A space saving is obtained, and increased freedom for placing the power supply contact window is obtained.
摘要翻译：当制造CMOS逻辑电路（例如反相器）时，通常需要将p沟道晶体管和n沟道晶体管的源极连接到它们各自的凹槽（分别为n和p）。现有技术需要覆盖源区域和桶区域的大的接触窗口，或者需要两个标准尺寸的接触窗口。本技术通过使用形成在源极/漏极区上的相同硅化物层（通常也在自对准硅化物（即“自对准硅化物”）工艺中也形成栅极硅化物）来形成接头连接。然后可以使用常规的窗口将硅化物浴盆连接件（因此源/桶区域）连接到电源导体。获得节省空间，并且获得放置电源接触窗口的增加的自由度。

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