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1. 发明授权

US5420987A Method and apparatus for configuring a selected adapter unit on a common bus in the presence of other adapter units 失效
标题翻译：用于在存在其它适配器单元的情况下在公共总线上配置所选择的适配器单元的方法和装置
公开(公告)号：US5420987A
公开(公告)日：1995-05-30
申请号：US93380
申请日：1993-07-19
申请人： Richard S. Reid , Niles Strohl , Glenn W. Connery , Paul W. Sherer , James P. Rivers
发明人： Richard S. Reid , Niles Strohl , Glenn W. Connery , Paul W. Sherer , James P. Rivers
IPC分类号： G06F13/14 , G06F9/445 , G06F15/177 , G06F13/00
CPC分类号： G06F9/4411 , G06F15/177
摘要： In a computer system having a central processing unit which employs software drivers as part of a host for controlling peripheral units and including a bus for connecting with adapters for the peripheral units, wherein each adapter has distributed intelligence means for interpreting simple command information and a nonvolatile storage element for storing default configuration information, including a default port address for communication, a method is provided for configuring such intelligent adapters connected to the bus. The method includes initializing the intelligent adapters by applying power to the bus or by issuing a global reset signal and causing a driver to be loaded by the central processing unit so that the host broadcasts a start key via a sequence of write commands via the bus to any adapters on the bus and to elicit responses from the intelligent adapters in an interactive manner to narrow communication between the intelligent adapters and the host to a single intelligent adapter without first specifying a unique port address. The narrowing process involves causing the intelligent adapters to first rank themselves for communication with the host by referring to unique ordered value information, e.g., an identification serial number, stored in the nonvolatile storage element, such as an EEPROM element, placed on the adapter.
摘要翻译：在具有中央处理单元的计算机系统中，所述中央处理单元采用软件驱动程序作为用于控制外围单元的主机的一部分，并且包括用于与用于外围单元的适配器连接的总线，其中每个适配器具有用于解释简单命令信息和非易失性存储器用于存储默认配置信息的存储元件，包括用于通信的默认端口地址，提供了用于配置连接到总线的这种智能适配器的方法。该方法包括：通过向总线施加电力或通过发出全局复位信号并使驱动器由中央处理单元加载来初始化智能适配器，使得主机经由总线经由一系列写入命令广播起始键到总线上的任何适配器，并以交互方式从智能适配器中引出响应，以将智能适配器和主机之间的通信精简到单个智能适配器，而无需首先指定唯一的端口地址。缩小过程包括使智能适配器首先通过参考放置在适配器上的诸如EEPROM元件之类的非易失性存储元件中存储的唯一的有序值信息（例如，识别序列号）来自己进行与主机的通信。

2. 发明授权

US5485584A Apparatus for simulating a stack structure using a single register and a counter to provide transmit status in a programmed I/O ethernet adapter with early interrupts 失效
标题翻译：用于使用单个寄存器和计数器模拟堆栈结构的装置，以在具有早期中断的编程I / O以太网适配器中提供发送状态
公开(公告)号：US5485584A
公开(公告)日：1996-01-16
申请号：US374491
申请日：1995-01-17
申请人： Richard Hausman , Paul W. Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
发明人： Richard Hausman , Paul W. Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
IPC分类号： G06F13/00 , G06F13/38 , H04L12/413 , H04L12/56 , H04L29/10 , G06F13/32
CPC分类号： H04L49/9068 , G06F13/385 , H04L12/40013 , H04L12/413 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9078 , H04L12/40032
摘要： In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
摘要翻译：在局域网（LAN）系统中，以太网适配器通过编程I / O（PIO）和FIFO缓冲器与主机交换数据。接收PIO采用DMA环形缓冲区备份，因此当PIO FIFO缓冲区已满时，传入的数据包可以直接复制到主机存储器中。当只有一部分分组已经从网络接收到时，适配器可以被编程为产生早期接收中断，以便减少等待时间。适配器也可以被编程为产生第二早期中断，使得将大数据包复制到主机可能重叠接收分组端。在数据包完全从主机传输到适配器之前，适配器开始分组传输，这进一步减少了延迟。适配器的最小延迟允许其使用足够小的接收和发送FIFO缓冲器，以将其包含在包含收发器，以太网控制器，FIFO控制电路和主机接口的专用集成电路（ASIC）内部的RAM内部。

3. 发明授权

US5412782A Programmed I/O ethernet adapter with early interrupts for accelerating data transfer 失效
标题翻译：带有早期中断的编程I / O以太网适配器，用于加速数据传输
公开(公告)号：US5412782A
公开(公告)日：1995-05-02
申请号：US907946
申请日：1992-07-02
申请人： Richard Hausman , Paul W. Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
发明人： Richard Hausman , Paul W. Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
IPC分类号： G06F13/00 , G06F13/38 , H04L12/413 , H04L12/56 , H04L29/10 , C06F13/00 , C06F13/38
CPC分类号： H04L49/9068 , G06F13/385 , H04L12/40013 , H04L12/413 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9078 , H04L12/40032
摘要： In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter may also be programmed to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
摘要翻译：在局域网（LAN）系统中，以太网适配器通过编程I / O（PIO）和FIFO缓冲器与主机交换数据。接收PIO采用DMA环形缓冲区备份，因此当PIO FIFO缓冲区已满时，传入的数据包可以直接复制到主机存储器中。当只有一部分分组已经从网络接收到时，适配器可以被编程为产生早期接收中断，以便减少等待时间。适配器也可以被编程为产生第二早期中断，使得将大数据包复制到主机可能重叠接收分组端。在将数据包从主机完全传输到适配器之前，适配器还可以被编程为开始分组传输，这进一步减少了等待时间。适配器的最小延迟允许其使用足够小的接收和发送FIFO缓冲器，以将其包含在包含收发器，以太网控制器，FIFO控制电路和主机接口的专用集成电路（ASIC）内部的RAM内部。

4. 发明授权

US08239580B2 Programmed I/O ethernet adapter with early interrupts for accelerating data transfer 失效
标题翻译：带有早期中断的编程I / O以太网适配器，用于加速数据传输
公开(公告)号：US08239580B2
公开(公告)日：2012-08-07
申请号：US12939604
申请日：2010-11-04
申请人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
发明人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
IPC分类号： G06F15/16 , G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00
CPC分类号： H04L49/9068 , G06F13/385 , H04L12/40013 , H04L12/40032 , H04L12/413 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9078
摘要： In a Local Area Network (LAN) system, an Ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
摘要翻译：在局域网（LAN）系统中，以太网适配器通过编程的I / O（PIO）和FIFO缓冲器与主机交换数据。接收PIO采用DMA环形缓冲区备份，因此当PIO FIFO缓冲区已满时，传入的数据包可以直接复制到主机存储器中。当只有一部分分组已经从网络接收到时，适配器可以被编程为产生早期接收中断，以便减少等待时间。适配器也可以被编程为产生第二早期中断，使得将大数据包复制到主机可能重叠接收分组端。在数据包完全从主机传输到适配器之前，适配器开始分组传输，这进一步减少了延迟。适配器的最小延迟允许其使用足够小的接收和发送FIFO缓冲器，以将其包含在包含收发器，以太网控制器，FIFO控制电路和主机接口的专用集成电路（ASIC）内部的RAM内部。

5. 发明授权

US07899937B1 Programmed I/O ethernet adapter with early interrupts for accelerating data transfer 失效
标题翻译：带有早期中断的编程I / O以太网适配器，用于加速数据传输
公开(公告)号：US07899937B1
公开(公告)日：2011-03-01
申请号：US09488942
申请日：2000-01-21
申请人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
发明人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
IPC分类号： G06F15/16 , G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00
CPC分类号： H04L49/9078 , G06F13/385 , H04L12/40032 , H04L49/90 , H04L49/9068
摘要： In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
摘要翻译：在局域网（LAN）系统中，以太网适配器通过编程I / O（PIO）和FIFO缓冲器与主机交换数据。接收PIO采用DMA环形缓冲区备份，因此当PIO FIFO缓冲区已满时，传入的数据包可以直接复制到主机存储器中。当只有一部分分组已经从网络接收到时，适配器可以被编程为产生早期接收中断，以便减少等待时间。适配器也可以被编程为产生第二早期中断，使得将大数据包复制到主机可能重叠接收分组端。在数据包完全从主机传输到适配器之前，适配器开始分组传输，这进一步减少了延迟。适配器的最小延迟允许其使用足够小的接收和发送FIFO缓冲器，以将其包含在包含收发器，以太网控制器，FIFO控制电路和主机接口的专用集成电路（ASIC）内部的RAM内部。

6. 发明申请

US20110047302A1 PROGRAMMED I/O ETHERNET ADAPTER WITH EARLY INTERRUPTS FOR ACCELERATING DATA TRANSFER 失效
标题翻译：具有加速数据传输的早期中断的编程I / O以太网适配器
公开(公告)号：US20110047302A1
公开(公告)日：2011-02-24
申请号：US12939604
申请日：2010-11-04
申请人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
发明人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
IPC分类号： G06F13/28 , G06F5/00 , G06F13/24
CPC分类号： H04L49/9068 , G06F13/385 , H04L12/40013 , H04L12/40032 , H04L12/413 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9078
摘要： In a Local Area Network (LAN) system, an Ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
摘要翻译：在局域网（LAN）系统中，以太网适配器通过编程的I / O（PIO）和FIFO缓冲器与主机交换数据。接收PIO采用DMA环形缓冲区备份，因此当PIO FIFO缓冲区已满时，传入的数据包可以直接复制到主机存储器中。当只有一部分分组已经从网络接收到时，适配器可以被编程为产生早期接收中断，以便减少等待时间。适配器也可以被编程为产生第二早期中断，使得将大数据包复制到主机可能重叠接收分组端。在数据包完全从主机传输到适配器之前，适配器开始分组传输，这进一步减少了延迟。适配器的最小延迟允许其使用足够小的接收和发送FIFO缓冲器，以将其包含在包含收发器，以太网控制器，FIFO控制电路和主机接口的专用集成电路（ASIC）内部的RAM内部。

7. 发明授权

US6112252A Programmed I/O ethernet adapter with early interrupt and DMA control for accelerating data transfer 失效
标题翻译：带有早期中断的编程I / O以太网适配器，用于加速数据传输
公开(公告)号：US6112252A
公开(公告)日：2000-08-29
申请号：US28088
申请日：1998-02-23
申请人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
发明人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
IPC分类号： G06F13/00 , G06F13/38 , H04L12/413 , H04L12/56 , H04L29/10 , G06F13/32
CPC分类号： H04L49/9068 , G06F13/385 , H04L12/40013 , H04L12/413 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9078 , H04L12/40032
摘要： In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
摘要翻译：在局域网（LAN）系统中，以太网适配器通过编程I / O（PIO）和FIFO缓冲器与主机交换数据。接收PIO采用DMA环形缓冲区备份，因此当PIO FIFO缓冲区已满时，传入的数据包可以直接复制到主机存储器中。当只有一部分分组已经从网络接收到时，适配器可以被编程为产生早期接收中断，以便减少等待时间。适配器也可以被编程为产生第二早期中断，使得将大数据包复制到主机可能重叠接收分组端。在数据包完全从主机传输到适配器之前，适配器开始分组传输，这进一步减少了延迟。适配器的最小延迟允许其使用足够小的接收和发送FIFO缓冲器，以将其包含在包含收发器，以太网控制器，FIFO控制电路和主机接口的专用集成电路（ASIC）内部的RAM内部。

8. 发明授权

US5872920A Programmed I/O ethernet adapter with early interrupts for accelerating data transfer 失效
公开(公告)号：US5872920A
公开(公告)日：1999-02-16
申请号：US503797
申请日：1995-07-18
申请人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
发明人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
IPC分类号： G06F13/00 , G06F13/38 , H04L12/413 , H04L12/56 , H04L29/10 , G06F13/32
CPC分类号： H04L49/9068 , G06F13/385 , H04L12/40013 , H04L12/413 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9078 , H04L12/40032
摘要： In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter may also be programmed to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

9. 发明授权

US5875176A Network adaptor driver with destination based ordering 失效
标题翻译：网络适配器驱动程序与基于目的地的排序
公开(公告)号：US5875176A
公开(公告)日：1999-02-23
申请号：US850906
申请日：1997-05-02
申请人： William Paul Sherer , Glenn W. Connery
发明人： William Paul Sherer , Glenn W. Connery
IPC分类号： H04L12/413 , H04L12/46 , H04L12/56 , H04L29/06 , H04L29/08
CPC分类号： H04L47/263 , H04L12/4625 , H04L12/5693 , H04L29/06 , H04L47/2441 , H04L47/28 , H04L47/621 , H04L47/6225 , H04L49/9036 , H04L69/324
摘要： A network transmitter (driver or adaptor/driver combination reorders packets received for transmission from a higher layer protocol based on packet destinations. The invention reduces bottlenecks at the transmitter and potentially throughout network intermediate system. Destination based reordering may be accomplished through alternative methods, some alternatives taking into account the order at which packets to different destinations are queued by a higher layer protocol.
摘要翻译：网络发射机（驱动器或适配器/驱动器组合）基于分组目的地重新排序接收来自较高层协议的传输的分组。本发明减少了发射机处的瓶颈，并且潜在地遍及网络中间系统。基于目的地的重新排序可以通过替代方法来实现，一些考虑到不同目的地的分组到较高层协议排队的顺序的替代方案。

10. 发明授权

US5600823A Method for optimizing software for any one of a plurality of variant architectures 失效
标题翻译：用于优化多个变体架构中的任何一个的软件的方法
公开(公告)号：US5600823A
公开(公告)日：1997-02-04
申请号：US417840
申请日：1995-04-06
申请人： W. Paul Sherer , Glenn W. Connery , Scott A. Emery
发明人： W. Paul Sherer , Glenn W. Connery , Scott A. Emery
IPC分类号： G06F9/445 , G06F12/02 , G06F15/177
CPC分类号： G06F12/023 , G06F9/44547
摘要： A method allows a designer to implement software for a wide variety of variant host architectures, without excessive usage of host memory, nor sacrificing the capabilities of high end versions of the variant architectures available. The method is based on providing an initialization module of the software to host memory. A portion of the initialization module determines the host architecture. Based on the determined host architecture, the unneeded portions of the initialization module are freed, and the needed portions are relocated into a contiguous memory space to minimize host memory usage. Any location dependent entries in the needed portions of the program are then updated based on the relocation. The initialization module includes a plurality of code blocks, each of which is optimized to a particular variant architecture. When the variant architecture of the host is identified, those code blocks which are optimized to the identified host are selected and the other code blocks are freed. The selected blocks are then relocated to optimize host memory usage.
摘要翻译：一种方法允许设计人员为多种不同的主机架构实现软件，而不会过多地使用主机内存，也不会牺牲可用的变体架构的高端版本的功能。该方法基于提供软件的初始化模块来主机存储器。初始化模块的一部分确定主机架构。基于确定的主机架构，初始化模块的不需要的部分被释放，并且所需部分被重新定位到连续的存储器空间中以最小化主机存储器使用。然后根据重定位更新程序所需部分中的任何位置相关条目。初始化模块包括多个代码块，每个代码块针对特定的变体架构被优化。当识别主机的变体架构时，选择对识别的主机优化的代码块，并且释放其他代码块。然后重新定位所选择的块以优化主机内存使用。

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