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1. 发明授权

US07899937B1 Programmed I/O ethernet adapter with early interrupts for accelerating data transfer 失效
标题翻译：带有早期中断的编程I / O以太网适配器，用于加速数据传输
公开(公告)号：US07899937B1
公开(公告)日：2011-03-01
申请号：US09488942
申请日：2000-01-21
申请人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
发明人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
IPC分类号： G06F15/16 , G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00
CPC分类号： H04L49/9078 , G06F13/385 , H04L12/40032 , H04L49/90 , H04L49/9068
摘要： In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
摘要翻译：在局域网（LAN）系统中，以太网适配器通过编程I / O（PIO）和FIFO缓冲器与主机交换数据。接收PIO采用DMA环形缓冲区备份，因此当PIO FIFO缓冲区已满时，传入的数据包可以直接复制到主机存储器中。当只有一部分分组已经从网络接收到时，适配器可以被编程为产生早期接收中断，以便减少等待时间。适配器也可以被编程为产生第二早期中断，使得将大数据包复制到主机可能重叠接收分组端。在数据包完全从主机传输到适配器之前，适配器开始分组传输，这进一步减少了延迟。适配器的最小延迟允许其使用足够小的接收和发送FIFO缓冲器，以将其包含在包含收发器，以太网控制器，FIFO控制电路和主机接口的专用集成电路（ASIC）内部的RAM内部。

2. 发明授权

US06681244B1 System and method for operating a network adapter when an associated network computing system is in a low-power state 有权
标题翻译：当相关网络计算系统处于低功率状态时操作网络适配器的系统和方法
公开(公告)号：US06681244B1
公开(公告)日：2004-01-20
申请号：US09591579
申请日：2000-06-09
申请人： Patricia C. Cross , Glenn W. Connery , Christopher J. Duguay
发明人： Patricia C. Cross , Glenn W. Connery , Christopher J. Duguay
IPC分类号： G06F1516
CPC分类号： G06F1/3209 , H04L67/24 , H04L69/329
摘要： A system for operating a network interface adapter when an associated network computing system is in a low-power state. The system includes a host executing an operating system (OS) and having a host OS absent state while operating in the low-power state and a host OS present state while operating in a full-power state. When a message is received at the network interface adapter, the network adapter determines whether the host is in the OS present state or the OS absent state. The network adapter forwards the message to the host if it is in the OS present state, and determines the message type if the host is in the OS absent state. The network adapter may generate and transmit a response to the message based on the message type without unnecessarily transitioning the host to the OS present state.
摘要翻译：一种用于在相关网络计算系统处于低功率状态时操作网络接口适配器的系统。该系统包括执行操作系统（OS）的主机，并且在处于低功率状态的同时操作主机OS不在状态，并且在全功率状态下工作时主机OS呈现状态。当在网络接口适配器上接收到消息时，网络适配器确定主机是处于OS当前状态还是OS不存在状态。网络适配器如果处于OS当前状态则将消息转发给主机，并且如果主机处于OS缺失状态，则确定该消息类型。网络适配器可以基于消息类型生成并发送对消息的响应，而不必将主机过渡到OS当前状态。

3. 发明授权

US06397287B1 Method and apparatus for dynamic bus request and burst-length control 失效
标题翻译：用于动态总线请求和突发长度控制的方法和装置
公开(公告)号：US06397287B1
公开(公告)日：2002-05-28
申请号：US09238238
申请日：1999-01-27
申请人： David Robert Brown , Glenn W. Connery
发明人： David Robert Brown , Glenn W. Connery
IPC分类号： G06F1300
CPC分类号： G06F13/385
摘要： A network adapter is provided that controls the transfer of data between a host computer and a network medium in a manner which optimizes the amount of data transferred between the host computer and the buffer of the network adapter during a contemporaneous transfer of data between the network medium and the buffer. The network adapter optimizes the data transfer by dynamically determining when to make a bus request such that the buffer is capable of transferring a data packet of a particular target burst size at the end of an estimated latency period. The network adapter includes a buffer memory that transfers data between the host computer and the network medium and a buffer control logic that generates a first buffer data signal in response to the amount of data in the buffer memory. The adapter further includes a bus control logic that generates a second buffer data signal in response to previous transfers of data between the host computer and the network medium, and a dynamic bus request logic that asserts a bus request signal at a time responsive to the first and second buffer data signals to initiate an optimized data transfer between the host computer and the buffer memory during a contemporaneous transfer of data between the buffer memory and the network medium. In one instance, the target burst size is equal to the maximum amount of data transferred between the host computer and the buffer in a single transaction since the host computer has been powered on. Further, in one instance the estimated latency is set as the latency of the previous data transfer between the buffer and the host computer. 1. BACKGROUND OF THE INVENTION
摘要翻译：提供了一种网络适配器，其以在网络介质之间的同时数据传输期间优化在主计算机和网络适配器的缓冲器之间传送的数据量的方式来控制主计算机和网络介质之间的数据传输和缓冲区。网络适配器通过动态地确定何时进行总线请求来优化数据传输，使得缓冲器能够在估计的等待时间周期结束时传送特定目标突发大小的数据分组。网络适配器包括在主计算机和网络介质之间传送数据的缓冲存储器和响应于缓冲存储器中的数据量产生第一缓冲数据信号的缓冲器控制逻辑。适配器还包括总线控制逻辑，其响应于主计算机和网络介质之间的数据的先前传输而产生第二缓冲器数据信号，以及动态总线请求逻辑，其在响应于第一个时钟的时间断言总线请求信号以及第二缓冲器数据信号，以在缓冲存储器和网络介质之间的同时数据传送期间发起主计算机和缓冲存储器之间的优化的数据传输。在一种情况下，目标突发大小等于主计算机上电后单个事务中主机与缓冲区之间传输的最大数据量。此外，在一个实例中，将估计的等待时间设置为缓冲器和主机之间的先前数据传输的延迟。

4. 发明授权

US5459854A Method for optimizing software for any one of a plurality of variant architectures 失效
标题翻译：用于优化多个变体架构中的任何一个的软件的方法
公开(公告)号：US5459854A
公开(公告)日：1995-10-17
申请号：US727824
申请日：1991-07-09
申请人： W. Paul Sherer , Glenn W. Connery , Scott A. Emery
发明人： W. Paul Sherer , Glenn W. Connery , Scott A. Emery
IPC分类号： G06F9/445 , G06F12/02 , G06F9/24 , G06F15/177
CPC分类号： G06F12/023 , G06F9/44547
摘要： A method allows a designer to implement software for a wide variety of variant host architectures, without excessive usage of host memory, nor sacrificing the capabilities of high end versions of the variant architectures available. The method is based on providing an initialization module of the software to host memory. A portion of the initialization module determines the host architecture. Based on the determined host architecture, the unneeded portions of the initialization module are freed, and the needed portions are relocated into a contiguous memory space to minimize host memory usage. Any location dependent entries in the needed portions of the program are then updated based on the relocation. The initialization module includes a plurality of code blocks, each of which is optimized to a particular variant architecture. When the variant architecture of the host is identified, those code blocks which are optimized to the identified host are selected and the other code blocks are freed. The selected blocks are then relocated to optimize host memory usage.
摘要翻译：一种方法允许设计人员为多种不同的主机架构实现软件，而不会过多地使用主机内存，也不会牺牲可用的变体架构的高端版本的功能。该方法基于提供软件的初始化模块来主机存储器。初始化模块的一部分确定主机架构。基于确定的主机架构，初始化模块的不需要的部分被释放，并且所需部分被重新定位到连续的存储器空间中以最小化主机存储器使用。然后根据重定位更新程序所需部分中的任何位置相关条目。初始化模块包括多个代码块，每个代码块针对特定的变体架构被优化。当识别主机的变体架构时，选择对识别的主机优化的代码块，并且释放其他代码块。然后重新定位所选择的块以优化主机内存使用。

5. 发明授权

US5420987A Method and apparatus for configuring a selected adapter unit on a common bus in the presence of other adapter units 失效
标题翻译：用于在存在其它适配器单元的情况下在公共总线上配置所选择的适配器单元的方法和装置
公开(公告)号：US5420987A
公开(公告)日：1995-05-30
申请号：US93380
申请日：1993-07-19
申请人： Richard S. Reid , Niles Strohl , Glenn W. Connery , Paul W. Sherer , James P. Rivers
发明人： Richard S. Reid , Niles Strohl , Glenn W. Connery , Paul W. Sherer , James P. Rivers
IPC分类号： G06F13/14 , G06F9/445 , G06F15/177 , G06F13/00
CPC分类号： G06F9/4411 , G06F15/177
摘要： In a computer system having a central processing unit which employs software drivers as part of a host for controlling peripheral units and including a bus for connecting with adapters for the peripheral units, wherein each adapter has distributed intelligence means for interpreting simple command information and a nonvolatile storage element for storing default configuration information, including a default port address for communication, a method is provided for configuring such intelligent adapters connected to the bus. The method includes initializing the intelligent adapters by applying power to the bus or by issuing a global reset signal and causing a driver to be loaded by the central processing unit so that the host broadcasts a start key via a sequence of write commands via the bus to any adapters on the bus and to elicit responses from the intelligent adapters in an interactive manner to narrow communication between the intelligent adapters and the host to a single intelligent adapter without first specifying a unique port address. The narrowing process involves causing the intelligent adapters to first rank themselves for communication with the host by referring to unique ordered value information, e.g., an identification serial number, stored in the nonvolatile storage element, such as an EEPROM element, placed on the adapter.
摘要翻译：在具有中央处理单元的计算机系统中，所述中央处理单元采用软件驱动程序作为用于控制外围单元的主机的一部分，并且包括用于与用于外围单元的适配器连接的总线，其中每个适配器具有用于解释简单命令信息和非易失性存储器用于存储默认配置信息的存储元件，包括用于通信的默认端口地址，提供了用于配置连接到总线的这种智能适配器的方法。该方法包括：通过向总线施加电力或通过发出全局复位信号并使驱动器由中央处理单元加载来初始化智能适配器，使得主机经由总线经由一系列写入命令广播起始键到总线上的任何适配器，并以交互方式从智能适配器中引出响应，以将智能适配器和主机之间的通信精简到单个智能适配器，而无需首先指定唯一的端口地址。缩小过程包括使智能适配器首先通过参考放置在适配器上的诸如EEPROM元件之类的非易失性存储元件中存储的唯一的有序值信息（例如，识别序列号）来自己进行与主机的通信。

6. 发明授权

US08239580B2 Programmed I/O ethernet adapter with early interrupts for accelerating data transfer 失效
标题翻译：带有早期中断的编程I / O以太网适配器，用于加速数据传输
公开(公告)号：US08239580B2
公开(公告)日：2012-08-07
申请号：US12939604
申请日：2010-11-04
申请人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
发明人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
IPC分类号： G06F15/16 , G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00
CPC分类号： H04L49/9068 , G06F13/385 , H04L12/40013 , H04L12/40032 , H04L12/413 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9078
摘要： In a Local Area Network (LAN) system, an Ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
摘要翻译：在局域网（LAN）系统中，以太网适配器通过编程的I / O（PIO）和FIFO缓冲器与主机交换数据。接收PIO采用DMA环形缓冲区备份，因此当PIO FIFO缓冲区已满时，传入的数据包可以直接复制到主机存储器中。当只有一部分分组已经从网络接收到时，适配器可以被编程为产生早期接收中断，以便减少等待时间。适配器也可以被编程为产生第二早期中断，使得将大数据包复制到主机可能重叠接收分组端。在数据包完全从主机传输到适配器之前，适配器开始分组传输，这进一步减少了延迟。适配器的最小延迟允许其使用足够小的接收和发送FIFO缓冲器，以将其包含在包含收发器，以太网控制器，FIFO控制电路和主机接口的专用集成电路（ASIC）内部的RAM内部。

7. 发明授权

US5600823A Method for optimizing software for any one of a plurality of variant architectures 失效
标题翻译：用于优化多个变体架构中的任何一个的软件的方法
公开(公告)号：US5600823A
公开(公告)日：1997-02-04
申请号：US417840
申请日：1995-04-06
申请人： W. Paul Sherer , Glenn W. Connery , Scott A. Emery
发明人： W. Paul Sherer , Glenn W. Connery , Scott A. Emery
IPC分类号： G06F9/445 , G06F12/02 , G06F15/177
CPC分类号： G06F12/023 , G06F9/44547
摘要： A method allows a designer to implement software for a wide variety of variant host architectures, without excessive usage of host memory, nor sacrificing the capabilities of high end versions of the variant architectures available. The method is based on providing an initialization module of the software to host memory. A portion of the initialization module determines the host architecture. Based on the determined host architecture, the unneeded portions of the initialization module are freed, and the needed portions are relocated into a contiguous memory space to minimize host memory usage. Any location dependent entries in the needed portions of the program are then updated based on the relocation. The initialization module includes a plurality of code blocks, each of which is optimized to a particular variant architecture. When the variant architecture of the host is identified, those code blocks which are optimized to the identified host are selected and the other code blocks are freed. The selected blocks are then relocated to optimize host memory usage.
摘要翻译：一种方法允许设计人员为多种不同的主机架构实现软件，而不会过多地使用主机内存，也不会牺牲可用的变体架构的高端版本的功能。该方法基于提供软件的初始化模块来主机存储器。初始化模块的一部分确定主机架构。基于确定的主机架构，初始化模块的不需要的部分被释放，并且所需部分被重新定位到连续的存储器空间中以最小化主机存储器使用。然后根据重定位更新程序所需部分中的任何位置相关条目。初始化模块包括多个代码块，每个代码块针对特定的变体架构被优化。当识别主机的变体架构时，选择对识别的主机优化的代码块，并且释放其他代码块。然后重新定位所选择的块以优化主机内存使用。

8. 发明申请

US20110047302A1 PROGRAMMED I/O ETHERNET ADAPTER WITH EARLY INTERRUPTS FOR ACCELERATING DATA TRANSFER 失效
标题翻译：具有加速数据传输的早期中断的编程I / O以太网适配器
公开(公告)号：US20110047302A1
公开(公告)日：2011-02-24
申请号：US12939604
申请日：2010-11-04
申请人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
发明人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
IPC分类号： G06F13/28 , G06F5/00 , G06F13/24
CPC分类号： H04L49/9068 , G06F13/385 , H04L12/40013 , H04L12/40032 , H04L12/413 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9078
摘要： In a Local Area Network (LAN) system, an Ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
摘要翻译：在局域网（LAN）系统中，以太网适配器通过编程的I / O（PIO）和FIFO缓冲器与主机交换数据。接收PIO采用DMA环形缓冲区备份，因此当PIO FIFO缓冲区已满时，传入的数据包可以直接复制到主机存储器中。当只有一部分分组已经从网络接收到时，适配器可以被编程为产生早期接收中断，以便减少等待时间。适配器也可以被编程为产生第二早期中断，使得将大数据包复制到主机可能重叠接收分组端。在数据包完全从主机传输到适配器之前，适配器开始分组传输，这进一步减少了延迟。适配器的最小延迟允许其使用足够小的接收和发送FIFO缓冲器，以将其包含在包含收发器，以太网控制器，FIFO控制电路和主机接口的专用集成电路（ASIC）内部的RAM内部。

9. 发明授权

US06606709B1 Secure system for remote management and wake-up commands 有权
标题翻译：用于远程管理和唤醒命令的安全系统
公开(公告)号：US06606709B1
公开(公告)日：2003-08-12
申请号：US10075103
申请日：2001-10-29
申请人： Glenn W. Connery , Danny M. Nessett
发明人： Glenn W. Connery , Danny M. Nessett
IPC分类号： G06F1130
CPC分类号： H04L63/08 , G06F1/26 , G06F1/3209 , H04L12/12 , H04L12/40032 , H04L12/413 , H04L63/0807 , H04L63/12 , Y02D50/40 , Y02D50/42
摘要： A security feature is added to the Wake On LAN packet protocol, and an extensible mechanism is provided allowing for other commands and options to be specified within the Wake On LAN packet. The protocol allows for signaling power management circuits in a host computer in response to messages received through a network interface. Logic coupled to the network interface detects a received network packet carrying a message from a source to the management circuits in the host computer. The logic includes security logic that is responsive to data in the packet to authenticate the source of the message, to accept the message and generate a signal to the management circuit in the host computer when the message passes authentication, and to discard the message when the message fails authentication. The message includes a message authentication code timestamp indicating a time at which the source produced the message and/or a random value token The security logic includes resources to verify the message authentication code and to prevent re-use of the message.
摘要翻译： Wake on LAN包协议中增加了一项安全功能，并提供了可扩展机制，允许在LAN唤醒包内指定其他命令和选项。该协议允许响应于通过网络接口接收的消息，在主计算机中发送信号功率管理电路。耦合到网络接口的逻辑检测从主机到主计算机中的管理电路的接收的网络分组携带消息。该逻辑包括响应于分组中的数据来认证消息源的安全逻辑，当消息通过认证时接受该消息并向主计算机中的管理电路生成信号，并且当该消息通过认证时丢弃该消息消息认证失败。消息包括指示源产生消息的时间和/或随机值令牌的消息认证码时间戳安全逻辑包括验证消息认证码并防止消息的重用的资源。

10. 发明授权

US6112252A Programmed I/O ethernet adapter with early interrupt and DMA control for accelerating data transfer 失效
标题翻译：带有早期中断的编程I / O以太网适配器，用于加速数据传输
公开(公告)号：US6112252A
公开(公告)日：2000-08-29
申请号：US28088
申请日：1998-02-23
申请人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
发明人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
IPC分类号： G06F13/00 , G06F13/38 , H04L12/413 , H04L12/56 , H04L29/10 , G06F13/32
CPC分类号： H04L49/9068 , G06F13/385 , H04L12/40013 , H04L12/413 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9078 , H04L12/40032
摘要： In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
摘要翻译：在局域网（LAN）系统中，以太网适配器通过编程I / O（PIO）和FIFO缓冲器与主机交换数据。接收PIO采用DMA环形缓冲区备份，因此当PIO FIFO缓冲区已满时，传入的数据包可以直接复制到主机存储器中。当只有一部分分组已经从网络接收到时，适配器可以被编程为产生早期接收中断，以便减少等待时间。适配器也可以被编程为产生第二早期中断，使得将大数据包复制到主机可能重叠接收分组端。在数据包完全从主机传输到适配器之前，适配器开始分组传输，这进一步减少了延迟。适配器的最小延迟允许其使用足够小的接收和发送FIFO缓冲器，以将其包含在包含收发器，以太网控制器，FIFO控制电路和主机接口的专用集成电路（ASIC）内部的RAM内部。

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