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1. 发明授权

US06750157B1 Nonvolatile memory cell with a nitridated oxide layer 有权
标题翻译：具有氮化氧化物层的非挥发性存储单元
公开(公告)号：US06750157B1
公开(公告)日：2004-06-15
申请号：US10199793
申请日：2002-07-19
申请人： Richard M. Fastow , Chi Chang , Narbeh Derhacobian
发明人： Richard M. Fastow , Chi Chang , Narbeh Derhacobian
IPC分类号： H01L2131
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/28282 , H01L21/3144 , H01L27/115 , H01L27/11568 , H01L29/513 , H01L29/518
摘要： One aspect of the present invention relates to a system and method for improving memory retention in flash memory devices. Retention characteristics may be enhanced by nitridating the bottom silicon dioxide layer of the ONO dielectric. To further mitigate charge leakage within the memory cell, the charge retention layer, or silicon nitride layer of the ONO dielectric, may be passivated via a hydrogen anneal process in order to reduce the number of charge traps, and thus, the amount of charge loss. The present invention also provides a monitoring and feedback-relay system to automatically control ONO formation such that a desired ONO dielectric stack is obtained. The present invention may be accomplished in part by employing a measurement system to measure properties and characteristics of the ONO stack during the critical formation steps of the bottom silicon dioxide layer and a silicon nitride layer.
摘要翻译：本发明的一个方面涉及用于改善闪存设备中的存储器保持的系统和方法。可以通过对ONO电介质的底部二氧化硅层进行氮化来增强保留特性。为了进一步减轻存储单元内的电荷泄漏，ONO电介质的电荷保持层或氮化硅层可以通过氢退火工艺被钝化，以减少电荷陷阱的数量，从而减少电荷损失量。本发明还提供了一种监测和反馈中继系统，用于自动控制ONO形成，从而获得所需的ONO电介质叠层。本发明可以部分地通过使用测量系统在底部二氧化硅层和氮化硅层的临界形成步骤期间测量ONO堆叠的性质和特性来实现。

2. 发明授权

US06549466B1 Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure 失效
标题翻译：使用以减少量的步骤施加的负栅极擦除电压以减少具有氧化物 - 氧化物 - 氧化物（ONO）结构的非易失性存储单元的擦除时间
公开(公告)号：US06549466B1
公开(公告)日：2003-04-15
申请号：US09657143
申请日：2000-09-07
申请人： Narbeh Derhacobian , Michael Van Buskirk , Chi Chang , Daniel Sobek
发明人： Narbeh Derhacobian , Michael Van Buskirk , Chi Chang , Daniel Sobek
IPC分类号： G11C1604
CPC分类号： G11C16/14
摘要： An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using a negative gate erase voltage during an erase procedure to improve the speed and performance of the non-volatile memory cell after many program-erase cycles. During the erase procedure, an erase cycle is applied followed by a read cycle until the cell has a threshold erased below a desired value. For the initial erase cycle in the procedure, an initial negative gate voltage is applied. In subsequent erase cycles, a sequentially decreasing negative gate voltage is applied until the threshold is reduced below the desired value. In one embodiment, after erase is complete, the last negative gate voltage value applied is stored in a separate memory. After a subsequent programming when the erase procedure is again applied, the initial negative gate voltage applied is the negative gate voltage value for the cell stored in memory.
摘要翻译：在擦除过程中通过使用负栅极擦除电压在具有氧化物 - 氮化物 - 氧化物结构的非易失性存储单元上执行擦除操作，以在许多编程擦除周期之后提高非易失性存储单元的速度和性能。在擦除过程期间，应用擦除周期，随后读取周期，直到单元具有低于期望值的阈值。对于程序中的初始擦除周期，施加初始负栅极电压。在随后的擦除周期中，施加顺序减小的负栅极电压，直到阈值降低到期望值以下。在一个实施例中，在擦除完成之后，施加的最后一个负栅极电压值被存储在单独的存储器中。在再次施加擦除过程之后的后续编程之后，施加的初始负栅极电压是存储在存储器中的单元的负栅极电压值。

3. 发明授权

US06356482B1 Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure 有权
标题翻译：使用负栅极擦除电压同时从具有氧化物 - 氧化物 - 氧化物（ONO）栅极结构的非易失性存储单元擦除两个位
公开(公告)号：US06356482B1
公开(公告)日：2002-03-12
申请号：US09657029
申请日：2000-09-07
申请人： Narbeh Derhacobian , Michael Van Buskirk , Chi Chang , Daniel Sobek
发明人： Narbeh Derhacobian , Michael Van Buskirk , Chi Chang , Daniel Sobek
IPC分类号： G11C1604
CPC分类号： G11C16/0416 , G11C16/14
摘要： An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure having charge stored near both the source and drain. During the erase operation, a negative gate erase voltage is applied along with a positive source and drain voltage to improve the speed of erase operations and performance of the non-volatile memory cell after many program-erase cycles.
摘要翻译：对具有存储在源极和漏极附近的电荷的氧化物 - 氧化物 - 氧化物结构的非易失性存储单元进行擦除操作。在擦除操作期间，施加负栅极擦除电压以及正的源极和漏极电压，以在许多编程擦除周期之后提高擦除操作的速度和非易失性存储单元的性能。

4. 发明授权

US06381179B1 Using a negative gate erase to increase the cycling endurance of a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure 有权
标题翻译：使用负栅极擦除来增加具有氧化物 - 氧化物 - 氧化物（ONO）结构的非易失性存储单元的循环耐久性
公开(公告)号：US06381179B1
公开(公告)日：2002-04-30
申请号：US09656675
申请日：2000-09-07
申请人： Narbeh Derhacobian , Michael Van Buskirk , Chi Chang , Daniel Sobek
发明人： Narbeh Derhacobian , Michael Van Buskirk , Chi Chang , Daniel Sobek
IPC分类号： G11C1604
CPC分类号： G11C16/14 , G11C16/0416
摘要： An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using an initial negative gate erase voltage to improve the speed and performance of the non-volatile memory cell after many program-erase cycles. By utilizing a negative gate erase voltage, the cell does not require increased erase time to reduce the cell threshold and avoid incomplete erase conditions as the number of program-erase cycles increases.
摘要翻译：通过使用初始负栅极擦除电压对具有氧化物 - 氮化物 - 氧化物结构的非易失性存储单元进行擦除操作，以在许多编程擦除周期之后提高非易失性存储单元的速度和性能。通过利用负栅极擦除电压，随着编程擦除周期数的增加，单元不需要增加的擦除时间来减小单元阈值并避免不完全的擦除条件。

5. 发明授权

US06246610B1 Symmetrical program and erase scheme to improve erase time degradation in NAND devices 有权
标题翻译：对称编程和擦除方案，以改善NAND器件中的擦除时间退化
公开(公告)号：US06246610B1
公开(公告)日：2001-06-12
申请号：US09511652
申请日：2000-02-22
申请人： K. Michael Han , Joseph G. Pawletko , Narbeh Derhacobian , Chi Chang
发明人： K. Michael Han , Joseph G. Pawletko , Narbeh Derhacobian , Chi Chang
IPC分类号： G11C1604
CPC分类号： G11C16/14 , G11C16/10 , G11C16/30
摘要： A programming and erase method that extends erase time degradation of nonvolatile memory devices by using a constant erase voltage and a set of program voltages, where the average program voltage of the set of the program voltages is approximately equal to the constant erase voltage.
摘要翻译：一种编程和擦除方法，其通过使用恒定擦除电压和一组编程电压来延长非易失性存储器件的擦除时间劣化，其中编程电压组的平均编程电压近似等于恒定擦除电压。

6. 发明授权

US06961267B1 Method and device for programming cells in a memory array in a narrow distribution 有权
标题翻译：用于以窄分布编程存储器阵列中的单元的方法和装置
公开(公告)号：US06961267B1
公开(公告)日：2005-11-01
申请号：US10738301
申请日：2003-12-16
申请人： Richard M. Fastow , Lee E. Cleveland , Chi Chang
发明人： Richard M. Fastow , Lee E. Cleveland , Chi Chang
IPC分类号： G11C16/04 , G11C16/34
CPC分类号： G11C16/3468
摘要： Accurately programming a memory cell. A voltage is applied to a drain of the memory cell to program the cell. After applying the voltage, the cell is verified as to whether it is programmed to a desired level. The magnitude of the programming voltage is increased and applied to the drain, and the memory cell is re-verified for the desired level. This is repeated until the memory cell is programmed to the desired level. Additional memory cells are programmed in this fashion in order to program multiple memory cells in a narrow distribution around the desired level. The programming can be done one memory cell at a time or many cells can be programmed in parallel. Further a ramped programming voltage can applied to the gate of the memory cell(s), such that the ramped voltage to the gate and the ramped voltage to the drain both program the memory cell.
摘要翻译：准确编程存储单元。将电压施加到存储器单元的漏极以对单元进行编程。在施加电压之后，验证单元是否被编程到所需的电平。编程电压的大小被增加并施加到漏极，并且存储器单元被重新验证所需的电平。直到将存储单元编程到所需的电平为止。以这种方式对附加存储器单元进行编程，以便以围绕期望水平的窄分布来编程多个存储器单元。编程可以一次完成一个存储单元，或者可以并行编程多个单元。此外，斜坡编程电压可以施加到存储器单元的栅极，使得到栅极的斜坡电压和到漏极的斜坡电压都对存储器单元进行编程。

7. 发明授权

US07288809B1 Flash memory with buried bit lines 有权
标题翻译：闪存与埋位线
公开(公告)号：US07288809B1
公开(公告)日：2007-10-30
申请号：US10738322
申请日：2003-12-16
申请人： Richard M. Fastow , Chi Chang , Sheung Hee Park
发明人： Richard M. Fastow , Chi Chang , Sheung Hee Park
IPC分类号： H01L29/72
CPC分类号： H01L27/115 , H01L27/11521
摘要： A memory cell and a method of forming the same are described. The memory cell is formed on a substrate. The memory cell includes a floating gate that is formed at least in part within the substrate. A bit line region is formed within the substrate in proximity to the floating gate. Because of the configuration of the bit line and the floating gate, memory cells can be located closer to each other, increasing the density of memory cells in a memory array.
摘要翻译：描述了存储单元及其形成方法。存储单元形成在基板上。存储单元包括至少部分地形成在衬底内的浮栅。位于衬底内的位线区域靠近浮动栅极。由于位线和浮动栅的配置，存储单元可以位于彼此更靠近，增加了存储器阵列中存储单元的密度。

8. 发明授权

US06894925B1 Flash memory cell programming method and system 有权
标题翻译：闪存单元编程方法和系统
公开(公告)号：US06894925B1
公开(公告)日：2005-05-17
申请号：US10342585
申请日：2003-01-14
申请人： Sheunghee Park , Sameer S. Haddad , Chi Chang , Richard M. Fastow , Ming Sang Kwan , Zhigang Wang
发明人： Sheunghee Park , Sameer S. Haddad , Chi Chang , Richard M. Fastow , Ming Sang Kwan , Zhigang Wang
IPC分类号： G11C11/56 , G11C16/04 , H01L29/423 , H01L29/788
CPC分类号： G11C11/5621 , G11C16/0416 , H01L29/42324 , H01L29/7883
摘要： A flash memory cell programming system and method that facilitate efficient and quick operation of a flash memory cell by providing a biasable well (e.g., substrate) is presented. The biasable well flash memory cell enables increases in electrical field strengths in a manner that eases resistance to charge penetration of a dielectric barrier (e.g., oxide) around a charge trapping region (e.g., a floating gate). The present biasable well system and method also create a self convergence point that increase control during programming operations and reduces the chances of excessive correction for over erased memory cells. The biasing can assist hard programming to store information and/or soft programming to correct the effects of over-erasing. The biasing can also reduce stress on a drain voltage pump, reduce leakage current and reduce programming durations. Some implementations also include a biasable control gate component, biasable source component and biasable drain component.
摘要翻译：提出了一种闪存单元编程系统和方法，其通过提供可偏置的阱（例如，衬底）来促进闪存单元的有效和快速的操作。可偏置阱快闪存储器单元能够以减轻电荷俘获区域（例如浮栅）周围的电介质势垒（例如氧化物）的电荷穿透的方式增加电场强度。本发明的偏压井系统和方法还创建了一个自会聚点，从而在编程操作期间增加了控制，并降低了对擦除过的存储器单元过度校正的可能性。偏置可以帮助硬编程来存储信息和/或软编程以校正过度擦除的影响。偏置还可以减少漏极电压泵上的应力，减少泄漏电流并减少编程持续时间。一些实施方案还包括可偏置控制栅极分量，可偏置源分量和可偏置漏极分量。

9. 发明授权

US09106734B2 Computer system and processor having integrated phone functionality 有权
标题翻译：具有集成手机功能的计算机系统和处理器
公开(公告)号：US09106734B2
公开(公告)日：2015-08-11
申请号：US13584527
申请日：2012-08-13
申请人： Chi Chang
发明人： Chi Chang
IPC分类号： H04M11/00 , H04M1/247 , G06F3/02 , G06F3/023 , G06F3/0489
CPC分类号： H04M1/2473 , G06F3/021 , G06F3/023 , G06F3/0489
摘要： A computer system including telephone functionality. The computer system includes a first keyboard and a first display. The computer system also includes a processor having at least a first functional unit and a second functional unit, and further includes a phone portion. The computer system may operate in a first mode, a second mode, or a third mode. In the first mode, only the phone portion is activated, and the phone portion provides a functionality of placing and receiving phone calls without being removed from the computer system. In the second mode, the phone portion and first functional unit of the processor are activated. In the third mode, each of the phone portion, the first functional unit, and the second functional unit are activated.
摘要翻译：包括电话功能的计算机系统。计算机系统包括第一键盘和第一显示器。计算机系统还包括具有至少第一功能单元和第二功能单元的处理器，并且还包括电话部分。计算机系统可以在第一模式，第二模式或第三模式中操作。在第一模式中，只有电话部分被激活，并且电话部分提供放置和接收电话呼叫的功能，而不从计算机系统移除。在第二模式中，处理器的电话部分和第一功能单元被激活。在第三模式中，电话部分，第一功能单元和第二功能单元中的每一个被激活。

10. 发明授权

US08455268B2 Gate replacement with top oxide regrowth for the top oxide improvement 有权
标题翻译：门顶置换，顶部氧化物再生长，用于顶部氧化物改良
公开(公告)号：US08455268B2
公开(公告)日：2013-06-04
申请号：US11848515
申请日：2007-08-31
申请人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Rinji Sugino , Chi Chang , Huaqiang Wu
发明人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Rinji Sugino , Chi Chang , Huaqiang Wu
IPC分类号： H01L21/00 , H01L21/311
CPC分类号： H01L29/7923 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/7887
摘要： Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.
摘要翻译：提供了替换/重整存储单元的电荷存储元件周围的顶部氧化物的方法和提高存储单元的电荷存储元件周围的顶部氧化物的质量的方法。该方法可以包括从存储器单元去除第一顶部氧化物上的第一多晶硅; 从存储器单元中去除第一顶部氧化物; 以及在所述电荷存储元件周围形成第二顶部氧化物。可以通过氧化电荷存储元件的一部分或通过在电荷存储元件上形成牺牲层并将牺牲层氧化成第二顶部氧化物来形成第二顶部氧化物。

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