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1. 发明授权

US6072368A Phase locked loop unlock detector 有权
标题翻译：锁相环解锁检测器
公开(公告)号：US6072368A
公开(公告)日：2000-06-06
申请号：US176137
申请日：1998-10-21
申请人： Richard Leo Galbraith , Larry A. Navarro, Jr. , Todd Carter Truax
发明人： Richard Leo Galbraith , Larry A. Navarro, Jr. , Todd Carter Truax
IPC分类号： G11B20/14 , H03L7/14 , H03L7/191 , G11B5/00 , G11B27/10
CPC分类号： H03L7/191 , G11B20/1403 , H03L7/14
摘要： A phase locked loop unlock detector is provided for a data detection channel in a direct access storage device (DASD). The phase locked loop unlock detector includes a counter for generating a threshold reference relative to a reference signal. An unlock window generator is coupled to the counter for generating an unlock window signal. An unlock error detector is coupled to the unlock window generator for comparing a variable frequency signal with the unlock window signal.
摘要翻译：为直接访问存储设备（DASD）中的数据检测通道提供锁相环解锁检测器。锁相环解锁检测器包括用于相对于参考信号产生阈值参考的计数器。解锁窗口发生器耦合到计数器以产生解锁窗口信号。解锁错误检测器耦合到解锁窗口发生器，用于将可变频率信号与解锁窗口信号进行比较。

2. 发明授权

US5784010A Method and apparatus for implementing a set rate code for data channels with alternate 9-bit code words and 8-bit code words 失效
标题翻译：用于实现具有交替的9位代码字和8位代码字的数据通道的设定速率代码的方法和装置
公开(公告)号：US5784010A
公开(公告)日：1998-07-21
申请号：US794718
申请日：1997-02-03
申请人： Jonathan Darrel Coker , David Timothy Flynn , Richard Leo Galbraith , Todd Carter Truax
发明人： Jonathan Darrel Coker , David Timothy Flynn , Richard Leo Galbraith , Todd Carter Truax
IPC分类号： G11B20/14 , H03M7/00
CPC分类号： G11B20/1426 , G11B2020/1434 , G11B2020/1446
摘要： A data encoding method and apparatus are provided for implementing a predefined rate code, such as a 16/17 rate code for a data detection channel in a direct access storage device. A binary data stream is received and sequential symbols of the received binary data stream are identified. Sequential alternate symbols of the binary data stream are encoded into first codewords. Sequential alternate other symbols are encoded into second codewords. The alternating first and second codewords are sequentially combined. For a rate 16/17 rate code, the first codewords include 9-bit codewords and the second codewords include 8-bit codewords. The second 8-bit codewords are either raw symbols of the received binary data stream or remapped symbols of the received binary data stream. All likely error events are limited to within three consecutive bytes in a user data stream with a 16/17 rate code of the preferred embodiment.
摘要翻译：提供了一种数据编码方法和装置，用于实现诸如用于直接访问存储设备中的数据检测通道的16/17速率码的预定速率码。接收二进制数据流，并识别所接收的二进制数据流的顺序符号。二进制数据流的顺序替代符号被编码成第一码字。顺序替代的其他符号被编码成第二码字。交替的第一和第二码字被顺序组合。对于速率16/17速率码，第一码字包括9位码字，第二码字包括8位码字。第二个8位码字是接收的二进制数据流的原始符号或接收的二进制数据流的重新映射的符号。所有可能的错误事件被限制在具有优选实施例的16/17速率代码的用户数据流中的三个连续字节内。

3. 发明授权

US08300342B2 Multi-bit phase alignment for synchronization mark pattern matching 有权
标题翻译：用于同步标记模式匹配的多位相位对齐
公开(公告)号：US08300342B2
公开(公告)日：2012-10-30
申请号：US12150814
申请日：2008-04-30
申请人： Richard Leo Galbraith , Weldon Mark Hanson , Travis Roger Oenning , Todd Carter Truax
发明人： Richard Leo Galbraith , Weldon Mark Hanson , Travis Roger Oenning , Todd Carter Truax
IPC分类号： G11B5/09 , H04L27/06
CPC分类号： G11B20/10009 , G11B20/10027 , G11B20/10046 , G11B20/10055 , G11B20/10194 , G11B20/10212 , G11B20/10222 , G11B20/10296 , G11B20/14 , G11B2020/1287 , G11B2020/1476 , G11B2220/2516
摘要： Embodiments of the present invention relate to the detection of synchronization marks in data storage and retrieval. To detect a synchronization mark, embodiments of the present invention require both pattern matching and proper phase alignment, following a repeating synchronization field. According to one particular embodiment, proper phase alignment following a repeated four bit synchronization field, is utilized in conjunction with pattern matching, to identify a synchronization mark. By allowing a synchronization mark to be identified only with proper phase alignment at the earliest possible occurrence of the synchronization mark, accuracy of synchronization mark detection may be improved.
摘要翻译：本发明的实施例涉及数据存储和检索中的同步标记的检测。为了检测同步标记，在重复的同步字段之后，本发明的实施例需要模式匹配和适当的相位对准。根据一个特定实施例，在重复的四位同步字段之后的适当的相位对准与模式匹配结合使用以识别同步标记。通过允许在同步标记的最早可能出现的情况下仅通过适当的相位对准来识别同步标记，可以提高同步标记检测的精度。

4. 发明授权

US08599973B2 Detection of synchronization mark from output of matched filter upstream of Viterbi detector 有权
标题翻译：维特比检测器上游匹配滤波器输出同步标记检测
公开(公告)号：US08599973B2
公开(公告)日：2013-12-03
申请号：US12150822
申请日：2008-04-30
申请人： Richard Leo Galbraith , Weldon Mark Hanson , Travis Roger Oenning , Todd Carter Truax
发明人： Richard Leo Galbraith , Weldon Mark Hanson , Travis Roger Oenning , Todd Carter Truax
IPC分类号： H03D1/00 , H04L27/06
CPC分类号： G11B20/10046 , G11B20/10009 , G11B20/10027 , G11B20/10055 , G11B20/10212 , G11B20/10287 , G11B20/10296 , G11B20/1217 , G11B20/14 , G11B2020/1287 , G11B2220/2516 , H03M13/41 , H03M13/6343
摘要： Embodiments of the present invention relate to the detection of synchronization marks in data storage and retrieval. According to one embodiment, synchronization marks are detected from the output of a matched filter, upstream of the Viterbi detector. This approach avoids the delay associated with the latency of the Viterbi output, thereby allowing time to align parity framing and to properly start the time-varying trellis. Certain embodiments disclose 34- and 20-bit primary synchronization marks located at the beginning of a data region. Other embodiments disclose 16-, 20-, and 24-bit embedded synchronization marks located within a data region.
摘要翻译：本发明的实施例涉及数据存储和检索中的同步标记的检测。根据一个实施例，从维特比检测器上游的匹配滤波器的输出检测同步标记。这种方法避免了与维特比输出的等待时间相关联的延迟，从而允许时间对齐奇偶校验框架并正确启动时变网格。某些实施例公开了位于数据区开始处的34位和20位主同步标记。其他实施例公开了位于数据区域内的16位，20位和24位嵌入式同步标记。

5. 发明申请

US20090274028A1 Multi-bit phase alignment for synchronization mark pattern matching 有权
标题翻译：用于同步标记模式匹配的多位相位对齐
公开(公告)号：US20090274028A1
公开(公告)日：2009-11-05
申请号：US12150814
申请日：2008-04-30
申请人： Richard Leo Galbraith , Weldon Mark Hanson , Travis Roger Oenning , Todd Carter Truax
发明人： Richard Leo Galbraith , Weldon Mark Hanson , Travis Roger Oenning , Todd Carter Truax
IPC分类号： G11B20/14
CPC分类号： G11B20/10009 , G11B20/10027 , G11B20/10046 , G11B20/10055 , G11B20/10194 , G11B20/10212 , G11B20/10222 , G11B20/10296 , G11B20/14 , G11B2020/1287 , G11B2020/1476 , G11B2220/2516
摘要： Embodiments of the present invention relate to the detection of synchronization marks in data storage and retrieval. To detect a synchronization mark, embodiments of the present invention require both pattern matching and proper phase alignment, following a repeating synchronization field. According to one particular embodiment, proper phase alignment following a repeated four bit synchronization field, is utilized in conjunction with pattern matching, to identify a synchronization mark. By allowing a synchronization mark to be identified only with proper phase alignment at the earliest possible occurrence of the synchronization mark, accuracy of synchronization mark detection may be improved.
摘要翻译：本发明的实施例涉及数据存储和检索中的同步标记的检测。为了检测同步标记，在重复的同步字段之后，本发明的实施例需要模式匹配和适当的相位对准。根据一个特定实施例，在重复的四位同步字段之后的适当的相位对准与模式匹配结合使用以识别同步标记。通过允许在同步标记的最早可能出现的情况下仅通过适当的相位对准来识别同步标记，可以提高同步标记检测的精度。

6. 发明授权

US07010065B2 Method and apparatus for word synchronization with large coding distance and fault tolerance for PRML systems 失效
公开(公告)号：US07010065B2
公开(公告)日：2006-03-07
申请号：US09865877
申请日：2001-05-25
申请人： Roy Daron Cideciyan , Jonathan Darrel Coker , Evangelos S. Eleftheriou , Richard Leo Galbraith , Todd Carter Truax
发明人： Roy Daron Cideciyan , Jonathan Darrel Coker , Evangelos S. Eleftheriou , Richard Leo Galbraith , Todd Carter Truax
IPC分类号： H03D1/00
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/10175 , G11B20/10296 , G11B20/1403 , H04L7/041
摘要： A method and apparatus are provided for word synchronization with large coding distance and fault tolerance for a partial-response maximum-likelihood (PRML) data channel in a direct access storage device (DASD). A Viterbi detector receives equalized PR4 samples including a predefined word synchronization pattern. The Viterbi detector is a dedicated detector optimized for detecting the predefined word synchronization pattern. The Viterbi detector includes a two-state Viterbi trellis and a word synchronization detector for the two-state Viterbi trellis. The predefined word synchronization pattern includes only even length magnets. The predefined word synchronization pattern is a repetition code including pairs of ones and pairs of zeros and includes multiple pattern match sequences. The Viterbi detector is optimized with branches removed from the Viterbi trellis, thus increasing coding distance. The two-state Viterbi trellis and word synchronization detector of the Viterbi detector operate on a 2T basis, where 1/T is the sample rate.

7. 发明授权

US06583941B1 Method and apparatus for thermal asperity recovery for word sync detection in data channels 有权
标题翻译：用于数据通道中字同步检测的热粗糙度恢复的方法和装置
公开(公告)号：US06583941B1
公开(公告)日：2003-06-24
申请号：US09522111
申请日：2000-03-09
申请人： Jonathan Darrel Coker , Richard Leo Galbraith , Todd Carter Truax , Donald Earl Vosberg
发明人： Jonathan Darrel Coker , Richard Leo Galbraith , Todd Carter Truax , Donald Earl Vosberg
IPC分类号： G11B509
CPC分类号： G11B20/24 , G11B5/09 , G11B20/1403 , G11B27/3027 , G11B27/36 , G11B2220/20
摘要： A method and apparatus are provided for thermal asperity recovery for word sync detection in data channels. A word sync field contains a plurality of word sync patterns. A word sync detector receives a read signal of the word sync field. The word sync detector identifies a first subset of the plurality of word sync patterns and starts a customer data read. When the word sync detector fails to identify the first subset of the plurality of word sync patterns, the read signal of the word sync field is received again. Then the word sync detector identifies a second predefined subset of the plurality of word sync patterns and starts a customer data read. A single word sync field is used instead of the conventional dual word sync fields required for each sector. The second predefined subset of the plurality of word sync patterns is smaller than the first subset. For example, when the first subset is defined as 4 of 8, the second predefined subset is 2 of 8. For example, when the first subset is defined as 6 of 12, the second predefined subset is 2 of 12.
摘要翻译：提供了一种用于数据通道中的词同步检测的热凹凸恢复的方法和装置。字同步字段包含多个字同步模式。字同步检测器接收字同步字段的读信号。字同步检测器识别多个字同步模式的第一子集，并开始客户数据读取。当字同步检测器不能识别多个字同步模式的第一子集时，再次接收字同步字段的读信号。然后，字同步检测器识别多个字同步模式的第二预定义子集，并开始客户数据读取。使用单个字同步字段而不是每个扇区所需的常规双字同步字段。多个字同步模式的第二预定义子集小于第一子集。例如，当第一子集被定义为8的4时，第二预定义子集是8的第二子集。例如，当第一子集被定义为12的第6子集时，第二预定义子集是12。

8. 发明申请

US20090274247A1 Detection of synchronization mark from output of matched filter upstream of viterbi detector 有权
标题翻译：从维特比检测器上游的匹配滤波器的输出检测同步标记
公开(公告)号：US20090274247A1
公开(公告)日：2009-11-05
申请号：US12150822
申请日：2008-04-30
申请人： Richard Leo Galbraith , Weldon Mark Hanson , Travis Roger Oenning , Todd Carter Truax
发明人： Richard Leo Galbraith , Weldon Mark Hanson , Travis Roger Oenning , Todd Carter Truax
IPC分类号： H03D1/00
CPC分类号： G11B20/10046 , G11B20/10009 , G11B20/10027 , G11B20/10055 , G11B20/10212 , G11B20/10287 , G11B20/10296 , G11B20/1217 , G11B20/14 , G11B2020/1287 , G11B2220/2516 , H03M13/41 , H03M13/6343
摘要： Embodiments of the present invention relate to the detection of synchronization marks in data storage and retrieval. According to one embodiment, synchronization marks are detected from the output of a matched filter, upstream of the Viterbi detector. This approach avoids the delay associated with the latency of the Viterbi output, thereby allowing time to align parity framing and to properly start the time-varying trellis. Certain embodiments disclose 34- and 20-bit primary synchronization marks located at the beginning of a data region. Other embodiments disclose 16-, 20-, and 24-bit embedded synchronization marks located within a data region.
摘要翻译：本发明的实施例涉及数据存储和检索中的同步标记的检测。根据一个实施例，从维特比检测器上游的匹配滤波器的输出检测同步标记。这种方法避免了与维特比输出的等待时间相关联的延迟，从而允许时间对齐奇偶校验框架并正确启动时变网格。某些实施例公开了位于数据区开始处的34位和20位主同步标记。其他实施例公开了位于数据区域内的16位，20位和24位嵌入式同步标记。

9. 发明授权

US08422296B2 Early detection of degradation in NAND flash memory 失效
标题翻译：早期检测NAND闪存中的劣化
公开(公告)号：US08422296B2
公开(公告)日：2013-04-16
申请号：US12930016
申请日：2010-12-22
申请人： Luiz M. Franca-Neto , Richard Leo Galbraith , Travis Roger Oenning
发明人： Luiz M. Franca-Neto , Richard Leo Galbraith , Travis Roger Oenning
IPC分类号： G11C11/34
CPC分类号： G11C16/3495
摘要： Techniques for early detection of degradation in NAND Flash memories by measuring the dispersion of the threshold voltages (VT's), of a set (e.g. page) of NAND Flash memory cells during read operations are described. In an embodiment of the invention the time-to-completion (TTC) values for the read operation for the memory cells are used as a proxy for dispersion of the threshold voltages (VT's). A Dispersion Analyzer determines the dispersion of the set of TTC values. In one embodiment the delta between the maximum and minimum TTC values is used as the dispersion measurement. If the measured TTC dispersion differs by more than a selected amount from a reference dispersion value, a warning signal is provided to indicate that the page of memory has degraded. The warning signal can be used to take appropriate action such as moving the data to a new page.
摘要翻译：描述了在读取操作期间通过测量NAND闪存单元组（例如页面）的阈值电压（VT）的偏差来早期检测NAND闪存中的劣化的技术。在本发明的一个实施例中，用于存储器单元的读取操作的完成时间（TTC）值用作阈值电压（VT）的色散的代理。色散分析仪确定一组TTC值的色散。在一个实施例中，使用最大和最小TTC值之间的差值作为色散测量。如果测量的TTC色散比参考色散值差多于选定量，则提供警告信号以指示存储器页面已经劣化。警告信号可用于采取适当措施，例如将数据移动到新页面。

10. 发明授权

US07733591B2 Data storage device with data recovery process using fixed phase clocking for analog-to-digital conversion 失效
标题翻译：具有数据恢复过程的数据存储设备使用固定相位时钟进行模数转换
公开(公告)号：US07733591B2
公开(公告)日：2010-06-08
申请号：US11641322
申请日：2006-12-18
申请人： Kraig Bottemiller , Richard Leo Galbraith , Weldon Mark Hanson , Travis Roger Oenning , Michael Joseph Ross , Fuminori Sai
发明人： Kraig Bottemiller , Richard Leo Galbraith , Weldon Mark Hanson , Travis Roger Oenning , Michael Joseph Ross , Fuminori Sai
IPC分类号： G11B5/09 , G11B15/52 , G11B19/02 , G11B5/02 , G11B20/18
CPC分类号： G11B5/09 , G11B20/10055 , G11B20/10222 , G11B20/10481 , G11B20/10527 , G11B20/1403 , G11B2020/1062
摘要： The invention includes apparatus and methods that allow a data storage device perform an enhanced data recovery procedure (DRP) that includes obtaining a new digital sampling of the voltages for the failing unit of data by re-reading the analog signal and converting it to digital form using an analog-to-digital conversion (ADC) using a fixed phase clock signal. The data samples are re-interpolated using a programmable delay line. The digital values representing the voltages are stored a buffer so that the data can be processed repeatedly using varying parameters as part of the data recovery procedure. Optionally the samples stored in the buffer can be processed in the reverse direction (from end of sector to beginning of sector) without requiring modification of the standard Viterbi detector since it inherently works on data processed in either direction.
摘要翻译：本发明包括允许数据存储设备执行增强型数据恢复过程（DRP）的装置和方法，其包括通过重新读取模拟信号并将其转换为数字形式来获得用于数据故障单元的电压的新数字采样使用固定相位时钟信号的模数转换（ADC）。使用可编程延迟线重新插值数据采样。表示电压的数字值被存储在缓冲器中，使得可以使用变化的参数重复处理数据，作为数据恢复过程的一部分。可选地，存储在缓冲器中的样本可以在相反方向（从扇区的结束到扇区的开始）进行处理，而不需要修改标准维特比检测器，因为它固有地对在任一方向上处理的数据进行工作。

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