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1. 发明授权

US06967110B2 Sensitive test structure for assessing pattern anomalies 有权
标题翻译：用于评估模式异常的敏感测试结构
公开(公告)号：US06967110B2
公开(公告)日：2005-11-22
申请号：US10438651
申请日：2003-05-15
申请人： Richard L. Guldi , Howard Tigelaar , Anand Reddy
发明人： Richard L. Guldi , Howard Tigelaar , Anand Reddy
IPC分类号： H01L23/544 , H01L21/00
CPC分类号： H01L22/34
摘要： A subset test module and associated methodology for utilizing the same are disclosed that facilitate identification of process drift in semiconductor fabrication processing. A test wafer having a plurality of die formed thereon has a plurality of test modules formed within the die. The plurality of test modules are substantially the same from die to die, and the respective modules similarly include a plurality of test structures that are substantially the same from module to module. Corresponding test structures within respective modules on different die are inspected and compared to one another to find structures that are sensitive to process drift. One or more structures that experience differences from module to module on different die are utilized to develop one or more test modules that can be selectively located within production wafers and monitored to determine whether process drift and/or one or more other aberrant processing conditions are occurring.
摘要翻译：公开了一种用于利用其的子集测试模块和相关联的方法，其有助于识别半导体制造处理中的工艺漂移。具有形成在其上的多个模具的测试晶片具有在模具内形成的多个测试模块。多个测试模块从模具到芯片基本上相同，并且各个模块类似地包括从模块到模块基本上相同的多个测试结构。对不同模具内相应模块内的相应测试结构进行检查和比较，以找到对工艺漂移敏感的结构。利用在不同管芯上从模块到模块经历差异的一个或多个结构来开发一个或多个可选择性地位于生产晶片内并被监控的测试模块，以确定是否发生过程漂移和/或一个或多个其它异常处理条件。

2. 发明申请

US20060033503A1 Sensitive test structure for assessing pattern anomalies 审中-公开
标题翻译：用于评估模式异常的敏感测试结构
公开(公告)号：US20060033503A1
公开(公告)日：2006-02-16
申请号：US11199664
申请日：2005-08-09
申请人： Richard Guldi , Howard Tigelaar , Anand Reddy
发明人： Richard Guldi , Howard Tigelaar , Anand Reddy
IPC分类号： H01L21/00 , G01R31/00
CPC分类号： H01L22/34
摘要： A subset test module and associated methodology for utilizing the same are disclosed that facilitate identification of process drift in semiconductor fabrication processing. A test wafer having a plurality of die formed thereon has a plurality of test modules formed within the die. The plurality of test modules are substantially the same from die to die, and the respective modules similarly include a plurality of test structures that are substantially the same from module to module. Corresponding test structures within respective modules on different die are inspected and compared to one another to find structures that are sensitive to process drift. One or more structures that experience differences from module to module on different die are utilized to develop one or more test modules that can be selectively located within production wafers and monitored to determine whether process drift and/or one or more other aberrant processing conditions are occurring.
摘要翻译：公开了一种用于利用其的子集测试模块和相关联的方法，其有助于识别半导体制造处理中的工艺漂移。具有形成在其上的多个模具的测试晶片具有在模具内形成的多个测试模块。多个测试模块从模具到芯片基本上相同，并且各个模块类似地包括从模块到模块基本上相同的多个测试结构。对不同模具内相应模块内的相应测试结构进行检查和比较，以找到对工艺漂移敏感的结构。利用在不同管芯上从模块到模块经历差异的一个或多个结构来开发一个或多个可选择性地位于生产晶片内并被监控的测试模块，以确定是否发生过程漂移和/或一个或多个其它异常处理条件。

3. 发明申请

US20080057711A1 Reduction of punch-thru defects in damascene processing 有权
标题翻译：减少镶嵌加工中的穿孔缺陷
公开(公告)号：US20080057711A1
公开(公告)日：2008-03-06
申请号：US11511698
申请日：2006-08-29
申请人： Phillip Daniel Matz , Sopa Chevacharoenkul , Ching-Te Lin , Basab Chatterjee , Anand Reddy , Kenneth Joseph Newton , Ju-Ai Ruan
发明人： Phillip Daniel Matz , Sopa Chevacharoenkul , Ching-Te Lin , Basab Chatterjee , Anand Reddy , Kenneth Joseph Newton , Ju-Ai Ruan
IPC分类号： H01L21/44
CPC分类号： H01L21/76834 , H01L21/02063 , H01L21/02164 , H01L21/02274 , H01L21/02282 , H01L21/31116 , H01L21/31608 , H01L21/31625 , H01L21/76802 , H01L21/76814 , H01L21/76883
摘要： A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.
摘要翻译：制造半导体器件，同时减轻金属化层中的导电空隙形成。提供基板。第一电介质层形成在衬底上。在第一电介质层内形成导电沟槽。在第一介电层上形成蚀刻停止层。在蚀刻停止层上/上形成第二介电层。在器件上形成抗蚀剂掩模，并且在第二介电层中蚀刻通孔。抗蚀剂掩模通过灰过程去除。执行清洁处理，其减轻/减少蚀刻停止层的暴露部分上的表面电荷。采用附加的表面电荷还原技术。通孔开口填充有导电材料，并执行平面化处理以去除多余的填充材料。

4. 发明申请

US20150177784A1 PORTABLE COMPUTING DEVICE HAVING A MOVABLE STAND 有权
标题翻译：具有可移动支架的便携式计算设备
公开(公告)号：US20150177784A1
公开(公告)日：2015-06-25
申请号：US14139967
申请日：2013-12-24
申请人： Krishnakumar Varadarajan , Anand Reddy
发明人： Krishnakumar Varadarajan , Anand Reddy
IPC分类号： G06F1/16
CPC分类号： G06F1/166 , G06F1/1626
摘要： A portable computing device includes a body that has a display. A stand is connected to the body. The stand is operable to place the portable computing device in a viewing orientation in which the portable computing device rests on the stand or a carrying orientation in which the stand acts as a handle for lifting the portable computing device. A rotation device connected to the stand assists in positioning the display in a range of angles for viewing convenience.
摘要翻译：便携式计算设备包括具有显示器的主体。一个支架连接到身体。支架可操作以将便携式计算设备置于便携式计算设备放置在支架上的观察方向或支架方向上，其中支架用作提升便携式计算设备的手柄。连接到支架的旋转装置有助于将显示器定位在一定范围的角度以便于观看。

5. 发明授权

US07727885B2 Reduction of punch-thru defects in damascene processing 有权
标题翻译：减少镶嵌加工中的穿孔缺陷
公开(公告)号：US07727885B2
公开(公告)日：2010-06-01
申请号：US11511698
申请日：2006-08-29
申请人： Phillip Daniel Matz , Sopa Chevacharoenkul , Ching-Te Lin , Basab Chatterjee , Anand Reddy , Kenneth Joseph Newton , Ju-Ai Ruan
发明人： Phillip Daniel Matz , Sopa Chevacharoenkul , Ching-Te Lin , Basab Chatterjee , Anand Reddy , Kenneth Joseph Newton , Ju-Ai Ruan
IPC分类号： H01L21/44
CPC分类号： H01L21/76834 , H01L21/02063 , H01L21/02164 , H01L21/02274 , H01L21/02282 , H01L21/31116 , H01L21/31608 , H01L21/31625 , H01L21/76802 , H01L21/76814 , H01L21/76883
摘要： A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.
摘要翻译：制造半导体器件，同时减轻金属化层中的导电空隙形成。提供基板。第一电介质层形成在衬底上。在第一电介质层内形成导电沟槽。在第一介电层上形成蚀刻停止层。在蚀刻停止层上/上形成第二介电层。在器件上形成抗蚀剂掩模，并且在第二介电层中蚀刻通孔。抗蚀剂掩模通过灰过程去除。执行清洁处理，其减轻/减少蚀刻停止层的暴露部分上的表面电荷。采用附加的表面电荷还原技术。通孔开口填充有导电材料，并执行平面化处理以去除多余的填充材料。

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