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1. 发明授权

US06798000B2 Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US06798000B2
公开(公告)日：2004-09-28
申请号：US10275337
申请日：2002-12-18
申请人： Richard Johannes Luyken , Till Schlösser , Thomas Peter Haneder , Wolfgang Hönlein , Franz Kreupl
发明人： Richard Johannes Luyken , Till Schlösser , Thomas Peter Haneder , Wolfgang Hönlein , Franz Kreupl
IPC分类号： H01L2976
CPC分类号： H01L51/0595 , B82Y10/00 , G11C2213/17 , H01L51/0048 , H01L51/0508 , Y10S977/938
摘要： A field-effect transistor that having a nanowire, which forms a source region, a channel region and a drain region of the field-effect transistor, the nanowire being a semiconducting and/or metallically conductive nanowire. The field-effect transistor also has at least one nanotube, which forms a gate region of the field-effect transistor, the nanotube being a semiconducting and/or metallically conductive nanotube. The nanowire and the nanotube are arranged at a distance from one another or set up in such a manner that it is substantially impossible for there to be a tunneling current between the nanowire and the nanotube, and that the conductivity of the channel region of the nanowire can be controlled by means of a field effect as a result of an electric voltage being applied to the nanotube.
摘要翻译：具有纳米线的场效应晶体管，其形成场效应晶体管的源极区，沟道区和漏极区，纳米线是半导体和/或金属导电的纳米线。场效应晶体管还具有形成场效应晶体管的栅极区域的至少一个纳米管，纳米管是半导体和/或金属导电的纳米管。纳米线和纳米管彼此间隔一定距离或以这样的方式设置，使得在纳米线和纳米管之间基本上不可能存在隧穿电流，并且纳米线的沟道区的导电性可以通过施加到纳米管的电压的结果通过场效应来控制。

2. 发明授权

US06438022B2 Memory cell configuration 失效
标题翻译：内存单元配置
公开(公告)号：US06438022B2
公开(公告)日：2002-08-20
申请号：US09854259
申请日：2001-05-10
申请人： Till Schlösser , Wolfgang Krautschneider , Franz Hofmann , Thomas-Peter Haneder
发明人： Till Schlösser , Wolfgang Krautschneider , Franz Hofmann , Thomas-Peter Haneder
IPC分类号： G11C1122
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/11507
摘要： The memory cells of a memory cell configuration each have a selection transistor, a memory transistor and a ferroelectric capacitor. The selection transistor and the memory transistor are connected in series. The ferroelectric capacitor is connected between a control electrode of the memory transistor and a first terminal of the selection transistor.
摘要翻译：存储单元结构的存储单元分别具有选择晶体管，存储晶体管和铁电电容器。选择晶体管和存储晶体管串联连接。铁电电容器连接在存储晶体管的控制电极和选择晶体管的第一端子之间。

3. 发明授权

US07368752B2 DRAM memory cell 失效
标题翻译： DRAM存储单元
公开(公告)号：US07368752B2
公开(公告)日：2008-05-06
申请号：US10839800
申请日：2004-05-06
申请人： Richard J. Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Rösner , Till Schlösser , Michael Specht
发明人： Richard J. Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Rösner , Till Schlösser , Michael Specht
IPC分类号： H01L27/108 , H01L29/12 , H01L31/112
CPC分类号： H01L27/10823 , H01L27/10808 , H01L27/10826 , H01L27/10829 , H01L27/10891 , H01L29/7851
摘要： A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.
摘要翻译： DRAM存储单元设置有选择晶体管，该晶体管被水平地布置在半导体衬底表面处并且具有第一源极/漏极，第二源极/漏极，布置在第一和第二源极/漏极之间的沟道层在所述半导体基板中，沿着所述沟道层配置并与所述沟道层电绝缘的栅电极具有与所述第一电容电极绝缘的第一电容电极和第二电容电极的保持电容器，所述存储电容器的电容器电极与所述选择晶体管的源极/漏极之一导电地连接，并且在后侧具有半导体衬底电极，所述栅电极在至少两个相对的两侧包围所述沟道层。

4. 发明授权

US06822916B2 Read/write amplifier having vertical transistors for a DRAM memory 失效
标题翻译：具有用于DRAM存储器的垂直晶体管的读/写放大器
公开(公告)号：US06822916B2
公开(公告)日：2004-11-23
申请号：US09796207
申请日：2001-06-01
申请人： Alexander Frey , Werner Weber , Till Schlösser
发明人： Alexander Frey , Werner Weber , Till Schlösser
IPC分类号： G11C700
CPC分类号： H01L27/10894 , G11C11/4091 , H01L27/10876 , H01L27/10897
摘要： As a consequence of DRAM memory cell miniaturization, the available space for read/write amplifiers decreases in width from hitherto 4 bit line grids to 2 bit lines grids. Conventionally previously known read/write amplifiers cannot be accommodated on this reduced, still available space. Therefore, it has not been possible hitherto to provide read/write amplifiers arranged beside one another which would manage with the novel DRAM memory cell spacings. The principle underlying the invention is based on replacing at least some of the transistors of conventional design which are usually used for read/write circuits by “vertical transistors” in which the differently doped regions are arranged one above the other or practically one above the other. Compared with the use of conventional transistors, the use of vertical transistors saves enough space to ensure an arrangement of a read/write circuit in the grid even with a reduced grid width.
摘要翻译：作为DRAM存储单元小型化的结果，用于读/写放大器的可用空间从迄今为止的4位线栅格宽度减小到2位线栅格。常规的已知的读/写放大器不能适应这个缩小的仍然可用的空间。因此，到目前为止还不可能提供一个旁边配置的读/写放大器，这些放大器将利用新颖的DRAM存储器单元间隔进行管理。本发明的原理是基于将通常用于读/写电路的常规设计的至少一些晶体管替换为“垂直晶体管”，其中不同掺杂区域一个在另一个上方布置或实际上一个在另一个之上。与使用常规晶体管相比，垂直晶体管的使用节省了足够的空间，以确保即使在减小的栅格宽度的情况下也能在网格中布置读/写电路。

5. 发明授权

US06750098B2 Integrated semiconductor memory and fabrication method 有权
标题翻译：集成半导体存储器和制造方法
公开(公告)号：US06750098B2
公开(公告)日：2004-06-15
申请号：US10619970
申请日：2003-07-15
申请人： Till Schlösser , Dirk Manger
发明人： Till Schlösser , Dirk Manger
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10888 , H01L27/10891 , H01L29/66666
摘要： In semiconductor memories having a surrounding gate configuration, webs, i.e. vertical rectangular pillars made of substrate material, are formed at the surface of a semiconductor substrate and are surrounded by the gate electrodes in a lower region. Conventionally, it is not possible for word lines to make contact with the gate electrodes in the lower region of the webs without at the same time electrically influencing substrate regions at a higher level in the webs or short-circuiting bit lines from their sidewalls, unless complicated methods requiring additional lithography steps are used. A method for the self-aligning, selective contact-connection of the peripheral gate electrodes is performed with the aid of an insulation layer having a smaller layer thickness than the peripheral gate electrodes.
摘要翻译：在具有围绕栅极结构的半导体存储器中，在半导体衬底的表面上形成由衬底材料制成的腹板，即垂直矩形柱，并且在下部区域中由栅电极包围。通常，字线不可能与幅材的下部区域中的栅极电极接触，而不会同时在幅材或短路位线从其侧壁电位影响衬底区域的较高水平，除非使用需要额外光刻步骤的复杂方法。借助于具有比外围栅极电极更薄的层厚度的绝缘层来执行外围栅电极的自对准，选择性接触连接的方法。

6. 发明授权

US06512259B1 Capacitor with high-&egr; dielectric or ferroelectric material based on the fin stack principle 有权
标题翻译：基于鳍片堆叠原理的具有高ε电介质或铁电材料的电容器
公开(公告)号：US06512259B1
公开(公告)日：2003-01-28
申请号：US09863925
申请日：2001-05-23
申请人： Gerrit Lange , Till Schlösser
发明人： Gerrit Lange , Till Schlösser
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/88
摘要： A capacitor in a semiconductor configuration on a substrate includes a noble-metal-containing first capacitor electrode which is formed with a plurality of mutually spaced-apart lamellae. The lamellae are oriented substantially parallel to a surface of the substrate and are mechanically and electrically connected to one another on a flank by a support structure. The capacitor furthermore has a capacitor dielectric formed of high-∈ dielectric or ferroelectric material disposed on the first capacitor electrode. The capacitor also has a second capacitor electrode on the capacitor dielectric.
摘要翻译：在基板上的半导体结构中的电容器包括形成有多个相互间隔开的薄片的含贵金属的第一电容器电极。薄片基本上平行于基底的表面定向，并且在侧面通过支撑结构彼此机械地和电连接。电容器还具有由设置在第一电容器电极上的电介质或铁电材料中的高电介质形成的电容器电介质。电容器还在电容器电介质上具有第二电容器电极。

7. 发明授权

US06445609B2 Integrated DRAM memory cell and DRAM memory 有权
标题翻译：集成DRAM存储单元和DRAM存储器
公开(公告)号：US06445609B2
公开(公告)日：2002-09-03
申请号：US09801715
申请日：2001-03-09
申请人： Alexander Frey , Werner Weber , Till Schlösser
发明人： Alexander Frey , Werner Weber , Till Schlösser
IPC分类号： G11C1194
CPC分类号： H01L27/10882 , G11C11/4097 , H01L27/0207 , H01L27/10829 , H01L27/10885 , H01L27/10897
摘要： A DRAM memory (50) having a number of DRAM memory cells (51) is described, the memory cells (51) in each case having a storage capacitor (52) and a selection transistor (12) which are formed in the area of an at least essentially rectangular cell area (59), the cell areas (59) having a greater extent in the longitudinal direction (L) than in the width direction (B) and which are wired or can be wired to the cell periphery via a word line (56, 57) and a bit line (55). The word lines (56, 57) and the bit line (55) are conducted over the memory cells (51) and are at least essentially oriented perpendicularly to one another. To achieve, with increasing miniaturization of the DRAM memory patterns, during the transition from so-called “folded” bit line architectures to so-called “open” bit line architectures that the bit line grid, and thus also the grid of corresponding read/write amplifiers, varies linearly in scale with the longitudinal extent (L) of the memory cells (51), it is provided according to the invention that the bit lines (55) are now oriented perpendicularly to the longitudinal extent (L) of the memory cells (51) in the direction of the lateral extent (B) of the memory cells (51)
摘要翻译：描述了具有多个DRAM存储单元（51）的DRAM存储器（50），每个情况下的存储单元（51）具有存储电容器（52）和选择晶体管（12）至少基本上矩形的单元区域（59），所述单元区域（59）在纵向方向（L）上比在宽度方向（B）上具有更大的程度，并且它们被布线或可以经由字连接到单元周边线（56,57）和位线（55）。字线（56,57）和位线（55）在存储器单元（51）上传导，并且至少基本上彼此垂直定向。为了实现随着DRAM存储器模式的小型化，在从所谓的“折叠”位线结构转变到所谓的“开放”位线架构，即位线格栅，从而也是对应读/ 写放大器随着存储器单元（51）的纵向延伸（L）而在尺度上线性变化，根据本发明，提供了位线（55）垂直于存储器的纵向延伸（L）定向在存储单元（51）的横向范围（B）的方向上的单元（51）

8. 发明授权

US07268381B2 Memory cell with trench capacitor and vertical select transistor and an annular contact-making region formed between them 失效
标题翻译：具有沟槽电容器和垂直选择晶体管的存储单元和在它们之间形成的环形接触区域
公开(公告)号：US07268381B2
公开(公告)日：2007-09-11
申请号：US10486758
申请日：2002-07-12
申请人： Albert Birner , Matthias Goldbach , Till Schlösser
发明人： Albert Birner , Matthias Goldbach , Till Schlösser
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10876
摘要： The upper capacitor electrode of the trench capacitor is connected to an epitaxially grown source/drain region of the select transistor by a tubular, monocrystalline Si contact-making region. The gate electrode layer has an oval peripheral contour around the transistor, the oval peripheral contours of the gate electrode layers of memory cells arranged in a row along a word line forming overlap regions in order to increase the packing density.
摘要翻译：沟槽电容器的上电容器电极通过管状的单晶Si接触形成区域连接到选择晶体管的外延生长的源极/漏极区域。栅极电极层在晶体管周围具有椭圆形外围轮廓，存储单元的栅极电极层的椭圆形外围轮廓沿着字线排列成一行形成重叠区域，以增加堆积密度。

9. 发明授权

US06956260B2 Integrated semiconductor memory with wordlines conductively connected to one another in pairs 失效
标题翻译：集成半导体存储器，其字线彼此成对地导电连接
公开(公告)号：US06956260B2
公开(公告)日：2005-10-18
申请号：US10463019
申请日：2003-06-17
申请人： Dirk Manger , Till Schlösser , Martin Popp , Michael Sesterhenn
发明人： Dirk Manger , Till Schlösser , Martin Popp , Michael Sesterhenn
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10876 , H01L27/10891
摘要： In semiconductor memories, in particular DRAMs, the memory cells of which have vertical transistors at vertical lands formed from substrate material, gate electrodes are formed as spacers which run around the land. The gate electrodes of adjacent memory cells conventionally have to be retroactively connected to form word lines. It is known to fill spaces between adjacent lands with an oxide, with the result that the spacers are formed directly as word lines but only cover two side walls of a land. Two transistors which are connected in parallel are formed at these side walls instead of a single transistor, since the gate electrode does not run around the land. The invention proposes a method for fabricating a semiconductor memory in which all four side walls of a land are covered by the word lines and at the same time lands of adjacent memory cells are connected to one another by the word lines.
摘要翻译：在半导体存储器中，特别是DRAM，其存储单元在由衬底材料形成的垂直焊盘处具有垂直晶体管，栅电极形成为围绕焊盘运行的间隔件。相邻存储单元的栅电极通常必须追溯地连接以形成字线。已知用相邻的焊盘之间的空间填充氧化物，结果是间隔件直接形成为字线，而仅覆盖焊盘的两个侧壁。并联连接的两个晶体管形成在这些侧壁而不是单个晶体管，因为栅电极不会绕着焊盘运行。本发明提出一种半导体存储器的制造方法，其中，由字线覆盖焊盘的四个侧壁，同时通过字线将相邻存储单元的焊盘相互连接。

10. 发明授权

US06645822B2 Method for manufacturing a semiconductor circuit system 失效
公开(公告)号：US06645822B2
公开(公告)日：2003-11-11
申请号：US10062940
申请日：2002-01-31
申请人： Till Schlösser
发明人： Till Schlösser
IPC分类号： H01L2120
CPC分类号： H01L27/222 , B82Y10/00 , H01L43/12
摘要： To simplify a method for manufacturing a memory device having a multiplicity of MRAM cells in a crossing area of conductor elements, a method for manufacturing a semiconductor circuit system, in particular, a memory device or the like, having a plurality of memory cells includes the step of structuring each of the memory elements simultaneously with the structuring of the first and second conductor elements.

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