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1. 发明授权

US5994778A Surface treatment of low-k SiOF to prevent metal interaction 有权
标题翻译：表面处理低k SiOF以防止金属相互作用
公开(公告)号：US5994778A
公开(公告)日：1999-11-30
申请号：US157240
申请日：1998-09-18
申请人： Richard J. Huang , Guarionex Morales , Simon Chan
发明人： Richard J. Huang , Guarionex Morales , Simon Chan
IPC分类号： H01L21/316 , H01L23/532 , H01L23/522
CPC分类号： H01L21/02131 , H01L21/0214 , H01L21/02274 , H01L21/02332 , H01L21/0234 , H01L21/31629 , H01L23/5329 , H01L2924/0002 , Y10S257/915
摘要： A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen. It is further preferred that the treated surface be passivated. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielective layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.
摘要翻译：一种在制造半导体产品的方法中使用低选择性SiOF的方法，包括以下步骤：获得SiOF层; 并从SiOF层的表面上消耗氟。在优选的实施方案中，耗尽步骤包括用含有氢的等离子体处理SiOF层的表面的步骤。进一步优选的是，处理过的表面被钝化。本发明还包括一种半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中所述SiOF半导体层包括其一个边缘处的第一区域，该第一区域耗尽氟到预定深度。

2. 发明授权

US06281584B1 Integrated circuit with improved adhesion between interfaces of conductive and dielectric surfaces 有权
标题翻译：集成电路，具有改善导电和电介质表面界面之间的粘附性
公开(公告)号：US06281584B1
公开(公告)日：2001-08-28
申请号：US09373482
申请日：1999-08-12
申请人： Minh Van Ngo , Richard J. Huang , Guarionex Morales
发明人： Minh Van Ngo , Richard J. Huang , Guarionex Morales
IPC分类号： H01L2348
CPC分类号： H01L21/31629 , H01L21/76801 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.
摘要翻译：一种在制造半导体产品的方法中使用低电介质SiOF的方法，包括以下步骤：获得SiOF层，并从SiOF层的表面上消耗氟。在优选的实施方案中，耗尽步骤包括用含有氨的等离子体处理SiOF层的表面的步骤。进一步优选的是，经过处理的表面被亚硝酸盐等离子体钝化。本发明还包括半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中SiOF电介质层包括其一个边缘处的第一区域，该第一区域耗尽氟到预定深度。

3. 发明授权

US06444593B1 Surface treatment of low-K SiOF to prevent metal interaction 有权
标题翻译：表面处理低K SiOF以防止金属相互作用
公开(公告)号：US06444593B1
公开(公告)日：2002-09-03
申请号：US09373483
申请日：1999-08-12
申请人： Minh Van Ngo , Richard J. Huang , Guarionex Morales
发明人： Minh Van Ngo , Richard J. Huang , Guarionex Morales
IPC分类号： H01L21425
CPC分类号： H01L21/31629 , H01L21/02131 , H01L21/02274 , H01L21/02332 , H01L21/0234 , H01L21/02362 , H01L21/76801 , H01L21/76807 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which depleted of fluorine to a predetermined depth.
摘要翻译：一种在制造半导体产品的方法中使用低电介质SiOF的方法，包括以下步骤：获得SiOF层，并从SiOF层的表面上消耗氟。在优选的实施方案中，耗尽步骤包括用含有氨的等离子体处理SiOF层的表面的步骤。进一步优选的是，经过处理的表面被亚硝酸盐等离子体钝化。本发明还包括半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中所述SiOF电介质层包括其一个边缘处的第一区域，所述第一区域耗尽氟至预定深度。

4. 发明授权

US06335273B2 Surface treatment of low-K SiOF to prevent metal interaction 有权
标题翻译：表面处理低K SiOF以防止金属相互作用
公开(公告)号：US06335273B2
公开(公告)日：2002-01-01
申请号：US09443376
申请日：1999-11-19
申请人： Richard J. Huang , Guarionex Morales , Simon Chan
发明人： Richard J. Huang , Guarionex Morales , Simon Chan
IPC分类号： H01L214763
CPC分类号： H01L21/02131 , H01L21/0214 , H01L21/02274 , H01L21/02332 , H01L21/0234 , H01L21/31629 , H01L23/5329 , H01L2924/0002 , Y10S257/915 , H01L2924/00
摘要： A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen. It is further preferred that the treated surface be passivated. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielective layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.
摘要翻译：一种在制造半导体产品的方法中使用低选择性SiOF的方法，包括以下步骤：获得SiOF层; 并从SiOF层的表面上消耗氟。在优选的实施方案中，耗尽步骤包括用含有氢的等离子体处理SiOF层的表面的步骤。进一步优选的是，处理过的表面被钝化。本发明还包括一种半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中所述SiOF半导体层包括其一个边缘处的第一区域，该第一区域耗尽氟到预定深度。

5. 发明授权

US6100192A Method of forming high integrity tungsten silicide thin films 失效
标题翻译：形成高完整性硅化钨薄膜的方法
公开(公告)号：US6100192A
公开(公告)日：2000-08-08
申请号：US993892
申请日：1997-12-18
申请人： Guarionex Morales , Richard J. Huang
发明人： Guarionex Morales , Richard J. Huang
IPC分类号： H01L21/28 , H01L21/44
CPC分类号： H01L21/28052
摘要： Thin films of tungsten silicide are deposited by CVD on conductive lines under conditions controlled to minimize development of tensile stresses upon subsequent thermal processing, thereby reducing cracking and delamination. Embodiments include reducing the deposition temperature and/or adjusting the gas flow ratio of reactants, such that the as deposited tungsten silicide film does not undergo a significant increase in densification and/or crystallinity upon subsequent deposition of a polycrystalline silicon capping layer.
摘要翻译：在控制的条件下，通过CVD在导电线上沉积硅化钨薄膜，以便在随后的热处理时最小化拉伸应力的发展，从而减少开裂和分层。实施方案包括降低沉积温度和/或调节反应物的气体流动比，使得随后沉积多晶硅覆盖层时，沉积的硅化钨膜不会显着增加致密化和/或结晶度。

6. 发明授权

US06211074B1 Methods and arrangements for reducing stress and preventing cracking in a silicide layer 失效
标题翻译：降低应力并防止硅化物层开裂的方法和装置
公开(公告)号：US06211074B1
公开(公告)日：2001-04-03
申请号：US09076584
申请日：1998-05-12
申请人： Richard J. Huang , Guarionex Morales
发明人： Richard J. Huang , Guarionex Morales
IPC分类号： H01L214763
CPC分类号： H01L27/11521 , H01L21/32053 , H01L27/115
摘要： Methods and arrangements that increase the process control during the fabrication of the control gate configuration in a non-volatile memory semiconductor device are provided. The methods and arrangements effectively prevent cracks from developing within a tungsten suicide layer that is part of a control gate structure within a non-volatile memory cell. Cracks within the tungsten silicide layer can affect the performance of the memory cell by increasing the resistance of the control gate configuration. The methods and arrangements prevent cracking of the tungsten silicide layer by minimizing the relative difference between temperatures associated with the deposition of the tungsten suicide layer and deposition of a subsequent overlying cap layer.
摘要翻译：提供了在制造非易失性存储器半导体器件中的控制栅极配置期间增加过程控制的方法和布置。该方法和装置有效地防止在作为非易失性存储单元内的控制栅极结构的一部分的硅化钨层内发生裂纹。硅化钨层内的裂纹可以通过增加控制栅极配置的电阻来影响存储单元的性能。所述方法和装置通过使与硅化钨层的沉积相关的温度之间的相对差异和随后的上覆盖层的沉积最小化来防止硅化钨层的破裂。

7. 发明授权

US6030891A Vacuum baked HSQ gap fill layer for high integrity borderless vias 失效
标题翻译：真空烘烤HSQ间隙填充层，用于高完整性无边界通孔
公开(公告)号：US6030891A
公开(公告)日：2000-02-29
申请号：US993052
申请日：1997-12-18
申请人： Khanh Tran , Richard J. Huang , Guarionex Morales
发明人： Khanh Tran , Richard J. Huang , Guarionex Morales
IPC分类号： H01L21/3105 , H01L21/312 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76852 , H01L21/02134 , H01L21/02164 , H01L21/022 , H01L21/02282 , H01L21/3124 , H01L21/76814 , H01L21/76826 , H01L21/76843 , H01L21/31058 , Y10S438/958
摘要： Borderless vias are formed in electrical connection with a lower metal feature of a metal patterned later gap filled with HSQ. Vacuum baking is conducted before filling the through-hole to outgas water absorbed during solvent cleaning, thereby reducing void formation and improving via integrity. Embodiments include vacuum baking at a temperature of about 300.degree. C. to about 400.degree. C., for about 45 seconds to about 2 minutes, at a pressure of no greater than about 10.sup.-6 Torr, preferably in the same tool employed for depositing the barrier layer in filling the through-hole.
摘要翻译：无边界通孔形成为与填充有HSQ的金属图案化的后续间隙的下部金属特征电连接。在填充通孔之前进行真空烘烤以排出在溶剂清洗期间吸收的水，从而减少空隙形成并改进通过完整性。实施方案包括在约300℃至约400℃的温度下，在不大于约10 -6乇的压力下进行约45秒至约2分钟的真空烘烤，优选在用于沉积的相同工具中进行真空烘烤阻挡层填充通孔。

8. 发明申请

US20120007221A1 MASK FOR FORMING INTEGRATED CIRCUIT 有权
标题翻译：形成集成电路的掩模
公开(公告)号：US20120007221A1
公开(公告)日：2012-01-12
申请号：US13241810
申请日：2011-09-23
申请人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
发明人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
IPC分类号： H01L29/66 , C23F1/00
CPC分类号： H01L21/28123 , H01L21/0332 , H01L21/28035 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.
摘要翻译：形成集成电路的方法包括在导电材料层之上提供包括电介质材料的缓冲层，并在缓冲层上方提供一层掩模材料。掩模材料包括无定形碳。该方法还包括去除缓冲层的一部分和掩模材料层以形成掩模。根据掩模在导电材料层中形成特征。

9. 发明授权

US07521304B1 Method for forming integrated circuit 失效
标题翻译：集成电路形成方法
公开(公告)号：US07521304B1
公开(公告)日：2009-04-21
申请号：US10230775
申请日：2002-08-29
申请人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
发明人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L21/0332 , H01L21/28035 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.
摘要翻译：形成集成电路的方法包括在导电材料层之上提供包括电介质材料的缓冲层，并在缓冲层上方提供一层掩模材料。掩模材料包括无定形碳。该方法还包括去除缓冲层的一部分和掩模材料层以形成掩模。根据掩模在导电材料层中形成特征。

10. 发明授权

US06518646B1 Semiconductor device with variable composition low-k inter-layer dielectric and method of making 有权
标题翻译：具有可变组成的低k层间电介质的半导体器件及其制造方法
公开(公告)号：US06518646B1
公开(公告)日：2003-02-11
申请号：US09819615
申请日：2001-03-29
申请人： Dawn M. Hopper , Suzette K. Pangrle , Calvin T. Gabriel , Richard J. Huang , Lu You
发明人： Dawn M. Hopper , Suzette K. Pangrle , Calvin T. Gabriel , Richard J. Huang , Lu You
IPC分类号： H01L2358
CPC分类号： H01L21/76832 , H01L21/76801 , H01L21/76807 , H01L21/76822 , H01L21/76829 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Strong adhesion to doped low-k inter-layer dielectrics is provided by varying the composition of dopant near the surface layers of the inter-layer dielectric. The concentration of dopant is gradually increased from about zero atomic % at the interface between the inter-layer dielectric and semiconductor substrate to improve adhesion of the inter-layer dielectric to the semiconductor substrate. The concentration of dopant at the upper surface of the inter-layer dielectric is gradually decreased to about zero atomic % at the upper surface of the inter-layer dielectric film in order to improve adhesion of additional layers to the inter-layer dielectric.
摘要翻译：通过改变层间电介质的表面层附近掺杂剂的组成，提供了对掺杂低k层间电介质的强粘合性。掺杂剂的浓度在层间电介质和半导体衬底之间的界面处从约零原子％逐渐增加，以提高层间电介质与半导体衬底的粘合性。层间电介质的上表面的掺杂剂浓度在层间电介质膜的上表面逐渐降低至约零原子％，以提高附加层对层间电介质的附着力。

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