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1. 发明授权

US07822701B2 Lexicon generation methods, lexicon generation devices, and lexicon generation articles of manufacture 有权
标题翻译：词典生成方法，词汇生成装置和词汇生成制品
公开(公告)号：US07822701B2
公开(公告)日：2010-10-26
申请号：US11479522
申请日：2006-06-30
申请人： Richard J. Carter , Jonathon D. McCall , Paul D. Whitney , Michelle L. Gregory , Alan E. Turner , Elizabeth G. Hetzler , Amanda M. White , Christian Posse , Grant C. Nakamura
发明人： Richard J. Carter , Jonathon D. McCall , Paul D. Whitney , Michelle L. Gregory , Alan E. Turner , Elizabeth G. Hetzler , Amanda M. White , Christian Posse , Grant C. Nakamura
IPC分类号： G06N7/00
CPC分类号： G06F17/2735
摘要： Lexicon generation methods, computer implemented lexicon editing methods, lexicon generation devices, lexicon editors, and articles of manufacture are described according to some aspects. In one aspect, a lexicon generation method includes providing a seed vector indicative of occurrences of a plurality of seed terms within a plurality of text items, providing a plurality of content vectors indicative of occurrences of respective ones of a plurality of content terms within the text items, comparing individual ones of the content vectors with respect to the seed vector, and responsive to the comparing, selecting at least one of the content terms as a term of a lexicon usable in sentiment analysis of text.
摘要翻译：根据一些方面描述词汇生成方法，计算机实现的词典编辑方法，词典生成装置，词典编辑器和制品。在一个方面，词典生成方法包括提供表示多个文本项目中的多个种子项目的出现的种子矢量，提供表示文本内的多个内容项目中各个内容项目的出现次数的多个内容向量项目，比较各个内容向量相对于种子向量，并且响应于比较，将内容词中的至少一个选择为可用于文本的情感分析中的词典的术语。

2. 发明授权

US08681579B2 Programmable current-limited voltage buffer, integrated-circuit device and method for current-limiting a memory element 有权
标题翻译：可编程限流电压缓冲器，用于限流存储器元件的集成电路器件和方法
公开(公告)号：US08681579B2
公开(公告)日：2014-03-25
申请号：US13384885
申请日：2010-04-30
申请人： Richard J. Carter , Muhammad Shakeel Qureshi
发明人： Richard J. Carter , Muhammad Shakeel Qureshi
IPC分类号： G11C8/00
CPC分类号： G11C7/12 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0028 , G11C13/0069 , G11C27/005 , G11C27/024 , G11C2013/0073 , G11C2013/0078
摘要： A programmable current-limited voltage buffer. The programmable current-limited voltage buffer includes at least one current-bias circuit, an inverter, a write-current set control circuit, and an adaptive current limiter. The inverter is coupled to the current-bias circuit and a reference-voltage source, and is configured to couple a row line to either the current-bias circuit, or the reference-voltage source, in response to an input signal. The adaptive current limiter is coupled to the current-bias circuit and to the write-current set control circuit, and is configured to limit current flowing through the memory element in a write operation. An integrated circuit device is also provided, along with a method for current limiting a memory element during switching in an array of memory elements.
摘要翻译：可编程限流电压缓冲器。可编程限流电压缓冲器包括至少一个电流偏置电路，反相器，写入电流控制电路和自适应限流器。反相器耦合到电流偏置电路和参考电压源，并且被配置为响应于输入信号将行线耦合到电流偏置电路或参考电压源。自适应限流器耦合到电流偏置电路和写入电流设置控制电路，并且被配置为在写入操作中限制流过存储器元件的电流。还提供了一种集成电路器件，以及用于在切换存储元件阵列期间电流限制存储器元件的方法。

3. 发明申请

US20130267086A1 PASSIVATING POINT DEFECTS IN HIGH-K GATE DIELECTRIC LAYERS DURING GATE STACK FORMATION 有权
标题翻译：栅格堆叠形成过程中高K栅介质层的钝点缺陷
公开(公告)号：US20130267086A1
公开(公告)日：2013-10-10
申请号：US13439016
申请日：2012-04-04
申请人： Elke Erben , Martin Trentzsch , Richard J. Carter
发明人： Elke Erben , Martin Trentzsch , Richard J. Carter
IPC分类号： H01L21/28 , H01L21/31
CPC分类号： H01L29/517 , H01L21/02181 , H01L21/022 , H01L21/0228 , H01L21/28194 , H01L21/2822 , H01L29/513
摘要： Generally, the present disclosure is directed to techniques for improving the reliability of semiconductor devices with high-k gate dielectric layers by passivating point defects during the gate stack formation. One illustrative method disclosed herein includes performing a plurality of material deposition cycles to form a high-k dielectric layer above a semiconductor material layer, and introducing a passivating material into a gaseous precursor that is used for forming the high-k dielectric layer during at least one of the plurality of material deposition cycles.
摘要翻译：通常，本公开涉及用于通过在栅极堆叠形成期间的钝化点缺陷来提高具有高k栅极电介质层的半导体器件的可靠性的技术。本文公开的一种说明性方法包括执行多个材料沉积循环以在半导体材料层上方形成高k电介质层，以及将钝化材料引入到用于在至少形成高k介电层的气态前体中多个材料沉积循环中的一个。

4. 发明授权

US08095803B1 Protecting the privacy of files referenced by their hash 有权
标题翻译：保护其散列引用的文件的隐私
公开(公告)号：US08095803B1
公开(公告)日：2012-01-10
申请号：US11684534
申请日：2007-03-09
申请人： Richard J. Carter , Mark S. Miller , Alan H. Karp
发明人： Richard J. Carter , Mark S. Miller , Alan H. Karp
IPC分类号： G06F11/30 , G06F12/14
CPC分类号： G06F21/6245
摘要： A storage manager provides data privacy, while preserving the benefits provided by existing hash based storage systems. Each file is assigned a unique identifying code. Hashes of the content-derived chunks of the file are calculated based on the content of the chunk and the code identifying the file. When a request to store a chunk of data is received, it is determined whether a chunk associated with the hash has already been stored. Because hashes are based on privacy-preserving codes as well as content, chunks of duplicate copies of a file need not be stored multiple times, and yet privacy is preserved for content at a file level. In other embodiments, hashes indicating whether a given file is public and/or indicating the identity of the requesting user are also sent with storage requests. These additional hashes enable more robust transmission and storage efficiency, while still preserving privacy.
摘要翻译：存储管理器提供数据隐私，同时保留现有基于哈希的存储系统提供的优点。每个文件都被分配一个唯一的识别码。基于块的内容和识别文件的代码来计算文件的内容导出块的哈希。当接收到存储数据块的请求时，确定是否已经存储与散列相关联的块。由于哈希是基于隐私保护代码以及内容，文件的重复副本的块不需要多次存储，而是保留文件级内容的隐私。在其他实施例中，指示给定文件是公开的和/或指示请求用户的身份的散列也与存储请求一起发送。这些额外的哈希可以实现更强大的传输和存储效率，同时保持隐私。

5. 发明授权

US07884430B2 Isolated metal plug process for use in fabricating carbon nanotube memory cells 失效
标题翻译：用于制造碳纳米管记忆单元的隔离金属塞工艺
公开(公告)号：US07884430B2
公开(公告)日：2011-02-08
申请号：US12710477
申请日：2010-02-23
申请人： Richard J. Carter , Peter A. Burke , Verne C. Hornback , Thomas Rueckes , Claude L. Bertin
发明人： Richard J. Carter , Peter A. Burke , Verne C. Hornback , Thomas Rueckes , Claude L. Bertin
IPC分类号： H01L29/84
CPC分类号： H01H1/0094 , Y10S977/724 , Y10S977/732 , Y10S977/943
摘要： The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor.
摘要翻译：本发明涉及制造具有纳米管横杆元件的机电存储器单元的结构和方法。这种存储单元包括具有与晶体管电接触的接触的晶体管的衬底。第一支撑层形成在衬底上，其开口限定了电触点上方的下腔室。纳米管横杆元件布置成跨越下室。第二支撑层形成有开口，所述开口限定在所述下腔室上方的顶部腔室，所述顶部腔室包括延伸超出所述下部腔室的边缘以暴露所述第一支撑层的顶部表面的一部分的延伸区域。屋顶层覆盖顶部室的顶部，并且包括露出顶部室的延伸区域的一部分并且包括延伸到顶部层中的孔中以密封顶部和底部室的插塞的孔。存储单元还包括覆盖在横杆元件上的电极，使得电信号可以激活电极以吸引或排斥交叉开关元件以设置晶体管的存储状态。

6. 发明授权

US07723192B2 Integrated circuit long and short channel metal gate devices and method of manufacture 有权
标题翻译：集成电路长短通道金属栅极器件及其制造方法
公开(公告)号：US07723192B2
公开(公告)日：2010-05-25
申请号：US12048414
申请日：2008-03-14
申请人： Richard J. Carter , Michael J. Hargrove , George J. Kluth , John G. Pellerin
发明人： Richard J. Carter , Michael J. Hargrove , George J. Kluth , John G. Pellerin
IPC分类号： H01L21/8234
CPC分类号： H01L21/823456 , H01L21/28114 , H01L21/823468 , H01L29/4933 , H01L29/66545
摘要： A method is provided for manufacturing an integrated circuit including a short channel (SC) device and a long channel (LC) device each overlaid by an interlayer dielectric. The SC device has an SC gate stack and the LC device initially has a dummy gate. In one embodiment, the method includes the steps of removing the dummy gate to form an LC device trench, and depositing metal gate material over the SC device and the LC device. The metal gate material contacts the SC gate stack and substantially fills the LC device trench.
摘要翻译：提供了一种用于制造集成电路的方法，该集成电路包括短沟道（SC）器件和每个由层间电介质覆盖的长沟道（LC）器件。 SC器件具有SC栅极堆叠，LC器件最初具有虚拟栅极。在一个实施例中，该方法包括以下步骤：去除伪栅极以形成LC器件沟槽，以及在SC器件和LC器件上沉积金属栅极材料。金属栅极材料接触SC栅极堆叠并且基本上填充LC器件沟槽。

7. 发明授权

US07402770B2 Nano structure electrode design 有权
标题翻译：纳米结构电极设计
公开(公告)号：US07402770B2
公开(公告)日：2008-07-22
申请号：US11270104
申请日：2005-11-09
申请人： Sey-Shing Sun , Hemanshu D. Bhatt , Peter A. Burke , Richard J. Carter
发明人： Sey-Shing Sun , Hemanshu D. Bhatt , Peter A. Burke , Richard J. Carter
IPC分类号： H01H9/00 , G11C11/50 , H01L21/00 , H01L23/58
CPC分类号： G11C13/025 , B82Y10/00 , H01L51/0048 , H01L51/0595 , Y10S977/724
摘要： A microelectronic switch having a substrate layer, an electrically conductive switching layer formed on the substrate layer, an electrically conductive cavity layer formed on the switching layer, an electrically conductive cap layer formed on the cavity layer, the cap layer forming a first electrode and a second electrode that are physically and electrically separated one from another, and which both at least partially overlie the switching layer, and a cavity disposed between the switching layer and the second electrode, where the switching is layer is flexible to make electrical contact with the second electrode by flexing through the cavity upon selective application of an electrical bias.
摘要翻译：具有衬底层的微电子开关，形成在衬底层上的导电开关层，形成在开关层上的导电腔层，形成在腔层上的导电帽层，形成第一电极的帽层和第二电极在物理上和电气上彼此分离，并且至少部分地覆盖在开关层上，并且设置在开关层和第二电极之间的空腔，其中开关层是柔性的，以与第二电极电接触电极通过在选择性地施加电偏压时通过空腔弯曲。

8. 发明授权

US07376741B1 System for aborting response to client request if detecting connection between client server is closed by examining local server information 有权
标题翻译：如果通过检查本地服务器信息来关闭检测到客户端服务器之间的连接的客户端请求中止响应的系统
公开(公告)号：US07376741B1
公开(公告)日：2008-05-20
申请号：US09272810
申请日：1999-03-19
申请人： Richard J. Carter , Ludmila Cherkasova
发明人： Richard J. Carter , Ludmila Cherkasova
IPC分类号： G06F15/16
CPC分类号： H04L12/66 , G06F9/544 , H04L67/02 , H04L67/14
摘要： An HTTP server is programmed to detect timed-out client requests by inferring states of its client-server connections. These connections, being full-duplex, can each be viewed as including a client-to-server channel and a server-to-client channel. The state of the server-to-client channel can be inferred by examining local server information to determine whether the client-to-server channel is still established. The server processes a request by a client if the inferred state indicates that the server-to-client channel is still established, and the server terminates the client request if the inferred state indicates that the server-to-client channel is no longer established. Consequently, the server does not expend resources by processing timed-out or dead client requests.
摘要翻译： HTTP服务器被编程为通过推断其客户机 - 服务器连接的状态来检测定时客户端请求。这些全双工连接可以被视为包括客户端到服务器的通道和服务器到客户机的通道。可以通过检查本地服务器信息来确定客户端到服务器信道是否仍然建立来推断服务器到客户端信道的状态。如果推断的状态指示服务器到客户端信道仍然建立，则服务器处理客户端的请求，并且如果推断的状态指示服务器到客户端信道不再建立，则服务器终止客户端请求。因此，服务器不会通过处理超时或死机客户端请求来消耗资源。

9. 发明授权

US5091851A Fast multiple-word accesses from a multi-way set-associative cache memory 失效
标题翻译：来自多方式相关高速缓存存储器的快速多字信息
公开(公告)号：US5091851A
公开(公告)日：1992-02-25
申请号：US382158
申请日：1989-07-19
申请人： John F. Shelton , Richard J. Carter
发明人： John F. Shelton , Richard J. Carter
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0864 , G06F12/0886
摘要： A multi-way set-associative cache memory stores data in a plurality of random access memories. Data in the multi-way set-associative cache memory is organized in lines of data. The multi-way set-associative cache memory allows access of single words and allows access of multiple-words of a length specific to the multi-way set-associative cache memory. Within the plurality of random access memories, data are placed such that corresponding words of each line of data is placed in different random access memories. Further, each word from each multiple word is placed in different random access memories. For single word access, one word is accessed from one of the plurality of random access memories. For multiple-word access, one word from each of the plurality of random access memories is accessed.

10. 发明授权

US08658490B2 Passivating point defects in high-K gate dielectric layers during gate stack formation 有权
标题翻译：在栅叠层形成过程中，高K栅极电介质层的钝化点缺陷
公开(公告)号：US08658490B2
公开(公告)日：2014-02-25
申请号：US13439016
申请日：2012-04-04
申请人： Elke Erben , Martin Trentzsch , Richard J. Carter
发明人： Elke Erben , Martin Trentzsch , Richard J. Carter
IPC分类号： H01L21/316
CPC分类号： H01L29/517 , H01L21/02181 , H01L21/022 , H01L21/0228 , H01L21/28194 , H01L21/2822 , H01L29/513
摘要： Generally, the present disclosure is directed to techniques for improving the reliability of semiconductor devices with high-k gate dielectric layers by passivating point defects during the gate stack formation. One illustrative method disclosed herein includes performing a plurality of material deposition cycles to form a high-k dielectric layer above a semiconductor material layer, and introducing a passivating material into a gaseous precursor that is used for forming the high-k dielectric layer during at least one of the plurality of material deposition cycles.
摘要翻译：通常，本公开涉及用于通过在栅极堆叠形成期间的钝化点缺陷来提高具有高k栅极电介质层的半导体器件的可靠性的技术。本文公开的一种说明性方法包括执行多个材料沉积循环以在半导体材料层上方形成高k电介质层，以及将钝化材料引入到用于在至少形成高k介电层的气态前体中多个材料沉积循环中的一个。

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