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1. 发明授权

US07915122B2 Self-aligned cell integration scheme 失效
标题翻译：自对准单元集成方案
公开(公告)号：US07915122B2
公开(公告)日：2011-03-29
申请号：US11312849
申请日：2005-12-20
申请人： Richard J. Carter , Hemanshu D. Bhatt , Shiqun Gu , Peter A. Burke , James R. B. Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
发明人： Richard J. Carter , Hemanshu D. Bhatt , Shiqun Gu , Peter A. Burke , James R. B. Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
IPC分类号： H01L21/336
CPC分类号： H01L51/0018 , B82Y10/00 , H01L27/283 , H01L51/0048 , H01L51/0545 , Y10S977/742
摘要： A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.
摘要翻译：一种形成自对准逻辑单元的方法。在底部电极上形成纳米管层。在纳米管层上形成夹层。夹层覆盖纳米管层，从而保护纳米管层。在钳位层上形成电介质层。蚀刻介电层。钳位层提供蚀刻停止并保护纳米管层。用各向同性蚀刻剂蚀刻钳夹层，蚀刻介质层下方的夹层，产生电介质层的重叠，并引起钳位层和电介质层之间的自对准。在纳米管层上形成间隔层。除了围绕电介质层的边缘的环形部分之外，蚀刻间隔层。除了夹持层，电介质层和间隔层中的至少一个的部分以外，蚀刻纳米管层，从而导致夹紧层之间的自对准，与电介质层的重叠，间隔层，和纳米管层。

2. 发明授权

US07402770B2 Nano structure electrode design 有权
标题翻译：纳米结构电极设计
公开(公告)号：US07402770B2
公开(公告)日：2008-07-22
申请号：US11270104
申请日：2005-11-09
申请人： Sey-Shing Sun , Hemanshu D. Bhatt , Peter A. Burke , Richard J. Carter
发明人： Sey-Shing Sun , Hemanshu D. Bhatt , Peter A. Burke , Richard J. Carter
IPC分类号： H01H9/00 , G11C11/50 , H01L21/00 , H01L23/58
CPC分类号： G11C13/025 , B82Y10/00 , H01L51/0048 , H01L51/0595 , Y10S977/724
摘要： A microelectronic switch having a substrate layer, an electrically conductive switching layer formed on the substrate layer, an electrically conductive cavity layer formed on the switching layer, an electrically conductive cap layer formed on the cavity layer, the cap layer forming a first electrode and a second electrode that are physically and electrically separated one from another, and which both at least partially overlie the switching layer, and a cavity disposed between the switching layer and the second electrode, where the switching is layer is flexible to make electrical contact with the second electrode by flexing through the cavity upon selective application of an electrical bias.
摘要翻译：具有衬底层的微电子开关，形成在衬底层上的导电开关层，形成在开关层上的导电腔层，形成在腔层上的导电帽层，形成第一电极的帽层和第二电极在物理上和电气上彼此分离，并且至少部分地覆盖在开关层上，并且设置在开关层和第二电极之间的空腔，其中开关层是柔性的，以与第二电极电接触电极通过在选择性地施加电偏压时通过空腔弯曲。

3. 发明授权

US06955937B1 Carbon nanotube memory cell for integrated circuit structure with removable side spacers to permit access to memory cell and process for forming such memory cell 失效
标题翻译：用于集成电路结构的碳纳米管存储单元，其具有可拆卸侧面间隔件，以允许访问存储器单元和用于形成这种存储器单元的
公开(公告)号：US06955937B1
公开(公告)日：2005-10-18
申请号：US10917551
申请日：2004-08-12
申请人： Peter A. Burke , Sey-Shing Sun , Hong-Qiang Lu
发明人： Peter A. Burke , Sey-Shing Sun , Hong-Qiang Lu
IPC分类号： G11C13/02 , H01L21/00 , H01L27/10
CPC分类号： H01L27/10 , B82Y10/00 , G11C13/025 , G11C2213/16 , Y10S977/943
摘要： A carbon nanotube memory cell for an integrated circuit wherein a chamber is constructed in a layer of a dielectric material such as silicon nitride down to a first electrical contact. This chamber is filled with polysilicon. A layer of a carbon nanotube mat or ribbon is formed over the silicon nitride layer and the chamber. A dielectric material, such as an oxide layer, is formed over the nanotube strips and patterned to form an upper chamber down to the ribbon layer to permit the ribbon to move into the upper chamber or into the lower chamber. The upper chamber is then filled with polysilicon. A silicon nitride layer is formed over the oxide layer and a contact opening is formed down to the ribbon and filled with tungsten that is then patterned to form metal lines. Any exposed silicon nitride is removed. A polysilicon layer is formed over the tungsten lines and anisotropically etched to remove polysilicon on the horizontal surfaces but leave polysilicon sidewall spacers. A silicon oxide layer is deposited over the structure and also anisotropically etched forming silicon oxide sidewall spacers on the polysilicon sidewall spacers. The polysilicon is wet etched with an etchant selective to adjacent materials to remove the polysilicon sidewalls spacers and all of the polysilicon in the chambers. Silicon oxide is formed over the structure and into the upper portion of the openings to seal the now empty chambers. A passivation layer may then be formed.
摘要翻译：一种用于集成电路的碳纳米管存储单元，其中室被构造成电介质材料如氮化硅的层，直到第一电接触。这个房间里充满了多晶硅。在氮化硅层和室之上形成一层碳纳米管垫或带。在纳米管条之上形成电介质材料，例如氧化物层，并被图案化以形成一个向下到带状层的上部腔室，以使带状物移动到上部腔室或下部腔室中。然后，上部室充满多晶硅。在氧化物层上形成氮化硅层，并且向下形成接触开口，并且填充有钨，然后将其图案化以形成金属线。任何暴露的氮化硅被去除。在钨线上形成多晶硅层，并进行各向异性蚀刻以去除水平表面上的多晶硅，但留下多晶硅侧壁间隔物。在结构上沉积氧化硅层，并且还各向异性地蚀刻在多晶硅侧壁间隔物上形成氧化硅侧壁间隔物。用对相邻材料选择性的蚀刻剂湿式蚀刻多晶硅以去除多晶硅侧壁间隔物和室中的所有多晶硅。在结构上形成氧化硅并进入开口的上部，以密封现在的空腔。然后可以形成钝化层。

4. 发明授权

US06987059B1 Method and structure for creating ultra low resistance damascene copper wiring 有权
标题翻译：制造超低电阻大马士革铜线的方法和结构
公开(公告)号：US06987059B1
公开(公告)日：2006-01-17
申请号：US10641768
申请日：2003-08-14
申请人： Peter A. Burke , Hongqiang Lu , Sey-Shing Sun
发明人： Peter A. Burke , Hongqiang Lu , Sey-Shing Sun
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76831 , H01L21/76841
摘要： A low resistance copper damascene interconnect structure is formed by providing a thin dielectric film such as SiC or SiOC formed on the sidewalls of the via and trench structures to function as a copper diffusion barrier layer. The dielectric copper diffusion barrier formed on the bottom of the trench structure is removed by anisotropic etching to expose patterned metal areas. The residual dielectric thus forms a dielectric diffusion barrier film on the sidewalls of the structure, and coupled with the metal diffusion barrier subsequently formed in the trench, creates a copper diffusion barrier to protect the bulk dielectric from copper leakage.
摘要翻译：通过在通孔和沟槽结构的侧壁上形成诸如SiC或SiOC的薄介电膜来形成低电阻铜镶嵌互连结构，起到铜扩散阻挡层的作用。通过各向异性蚀刻去除在沟槽结构的底部形成的电介质铜扩散屏障，以露出图案化的金属区域。因此，残余电介质在结构的侧壁上形成电介质扩散阻挡膜，并与随后在沟槽中形成的金属扩散阻挡层耦合，形成铜扩散阻挡层，以保护大块电介质免受铜泄漏。

5. 发明授权

US07300869B2 Integrated barrier and seed layer for copper interconnect technology 有权
标题翻译：铜互连技术的集成屏障和种子层
公开(公告)号：US07300869B2
公开(公告)日：2007-11-27
申请号：US10945777
申请日：2004-09-20
申请人： Sey-Shing Sun , Byung-Sung L. Kwak , Peter A. Burke
发明人： Sey-Shing Sun , Byung-Sung L. Kwak , Peter A. Burke
IPC分类号： H01L21/4763 , H01L29/45
CPC分类号： H01L21/76844 , H01L21/76843 , H01L21/76846 , H01L21/76871 , H01L21/76873 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated barrier and seed layer that is useful for creating conductive pathways in semiconductor devices. The barrier portion of the integrated layer prevents diffusion of the conductive material into the underlying dielectric substrate while the seed portion provides an appropriate foundation upon which to deposit the conductive material. The barrier portion of the integrated layer is formed of a metal nitride, while the seed portion is formed of ruthenium or a ruthenium alloy. The metal nitride forms an effective barrier layer while the ruthenium or ruthenium alloy forms an effective seed layer for a metal such as copper. In some embodiments, the integrated layer is formed in a way so that its composition changes gradually from one region to the next.
摘要翻译：集成的屏障和种子层，可用于在半导体器件中产生导电通路。集成层的阻挡部分防止导电材料扩散到下面的电介质基底中，同时种子部分提供了沉积导电材料的适当基础。集成层的阻挡部分由金属氮化物形成，而种子部分由钌或钌合金形成。金属氮化物形成有效的阻挡层，而钌或钌合金形成金属如铜的有效晶种层。在一些实施例中，集成层以使其组成从一个区域逐渐变化到下一个区域的方式形成。

6. 发明授权

US07196420B1 Method and structure for creating ultra low resistance damascene copper wiring 有权
标题翻译：制造超低电阻大马士革铜线的方法和结构
公开(公告)号：US07196420B1
公开(公告)日：2007-03-27
申请号：US11259965
申请日：2005-10-26
申请人： Peter A. Burke , Hongqiang Lu , Sey-Shing Sun
发明人： Peter A. Burke , Hongqiang Lu , Sey-Shing Sun
IPC分类号： H01L23/48
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76831 , H01L21/76841
摘要： A low resistance copper damascene interconnect structure is formed by providing a thin dielectric film such as SiC or SiOC formed on the sidewalls of the via and trench structures to function as a copper diffusion barrier layer. The dielectric copper diffusion barrier formed on the bottom of the trench structure is removed by anisotropic etching to expose patterned metal areas. The residual dielectric thus forms a dielectric diffusion barrier film on the sidewalls of the structure, and coupled with the metal diffusion barrier subsequently formed in the trench, creates a copper diffusion barrier to protect the bulk dielectric from copper leakage.
摘要翻译：通过在通孔和沟槽结构的侧壁上形成诸如SiC或SiOC的薄介电膜来形成低电阻铜镶嵌互连结构，起到铜扩散阻挡层的作用。通过各向异性蚀刻去除在沟槽结构的底部形成的电介质铜扩散屏障，以露出图案化的金属区域。因此，残余电介质在结构的侧壁上形成电介质扩散阻挡膜，并与随后在沟槽中形成的金属扩散阻挡层耦合，形成铜扩散阻挡层，以保护大块电介质免受铜泄漏。

7. 发明授权

US07115425B2 Integrated circuit process monitoring and metrology system 有权
标题翻译：集成电路过程监控与计量系统
公开(公告)号：US07115425B2
公开(公告)日：2006-10-03
申请号：US11072127
申请日：2005-03-04
申请人： Peter A. Burke , Eric J. Kirchner , James R. B. Elmer
发明人： Peter A. Burke , Eric J. Kirchner , James R. B. Elmer
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , H01L21/31053
摘要： A method for monitoring polishing process parameters for an integrated circuit structure on a substrate. A first metrology site is constructed on the substrate. The first metrology site represents a design extreme of a high density integrated circuit structure. The first metrology site is formed by placing a relatively small horizontal surface area trench within a relatively large surface area field of a polish stop material. A second metrology site is also constructed on the substrate. The second metrology site represents a design extreme of a low density integrated circuit structure. The second metrology site is formed by placing a relatively large horizontal surface area trench within a relatively small surface area field of a polish stop material. The substrate is covered with a layer of an insulating material, thereby at least filling the trenches. A target thickness of the insulating material necessary to leave the trenches substantially filled to a top surface of the field of polish stop material is calculated. The substrate is polished until a first thickness of the insulating material in the trench of the first metrology site is no more than the target thickness. A second thickness of the insulating material in the trench of the second metrology site is measured, and values based on the first thickness and the second thickness are monitored as the polishing process parameters for the integrated circuit structure.
摘要翻译：一种用于监测基板上的集成电路结构的抛光工艺参数的方法。第一个计量站点被构建在基板上。第一个测量站点代表了高密度集成电路结构的设计极限。第一计量站点是通过在抛光停止材料的相对大的表面区域内放置相对较小的水平表面区域沟槽而形成的。第二个计量站点也在基板上构建。第二个测量站点是低密度集成电路结构的设计极限。第二计量站点通过在抛光停止材料的相对小的表面区域内放置相对较大的水平表面区域沟槽而形成。衬底被绝缘材料层覆盖，从而至少填充沟槽。计算出将沟槽基本上填充到抛光停止材料领域的顶表面所需的绝缘材料的目标厚度。抛光衬底直到第一测量点的沟槽中的绝缘材料的第一厚度不超过目标厚度。测量第二测量位置的沟槽中的绝缘材料的第二厚度，并且监测基于第一厚度和第二厚度的值作为用于集成电路结构的抛光工艺参数。

8. 发明授权

US06964924B1 Integrated circuit process monitoring and metrology system 失效
标题翻译：集成电路过程监控与计量系统
公开(公告)号：US06964924B1
公开(公告)日：2005-11-15
申请号：US09952790
申请日：2001-09-11
申请人： Peter A. Burke , Eric J. Kirchner , James R. B. Elmer
发明人： Peter A. Burke , Eric J. Kirchner , James R. B. Elmer
IPC分类号： H01L21/302 , H01L21/3105 , H01L21/66 , H01L21/76 , H01L23/544
CPC分类号： H01L22/34 , H01L21/31053
摘要： A method for monitoring polishing process parameters for an integrated circuit structure on a substrate. A first metrology site is constructed on the substrate. The first metrology site represents a design extreme of a high density integrated circuit structure. The first metrology site is formed by placing a relatively small horizontal surface area trench within a relatively large surface area field of a polish stop material. A second metrology site is also constructed on the substrate. The second metrology site represents a design extreme of a low density integrated circuit structure. The second metrology site is formed by placing a relatively large horizontal surface area trench within a relatively small surface area field of a polish stop material. The substrate is covered with a layer of an insulating material, thereby at least filling the trenches. A target thickness of the insulating material necessary to leave the trenches substantially filled to a top surface of the field of polish stop material is calculated. The substrate is polished until a first thickness of the insulating material in the trench of the first metrology site is no more than the target thickness. A second thickness of the insulating material in the trench of the second metrology site is measured, and values based on the first thickness and the second thickness are monitored as the polishing process parameters for the integrated circuit structure.
摘要翻译：一种用于监测基板上的集成电路结构的抛光工艺参数的方法。第一个计量站点被构建在基板上。第一个测量站点代表了高密度集成电路结构的设计极限。第一计量站点是通过在抛光停止材料的相对大的表面区域内放置相对较小的水平表面区域沟槽而形成的。第二个计量站点也在基板上构建。第二个测量站点是低密度集成电路结构的设计极限。第二计量站点通过在抛光停止材料的相对小的表面区域内放置相对较大的水平表面区域沟槽而形成。衬底被绝缘材料层覆盖，从而至少填充沟槽。计算出将沟槽基本上填充到抛光停止材料领域的顶表面所需的绝缘材料的目标厚度。抛光衬底直到第一测量点的沟槽中的绝缘材料的第一厚度不超过目标厚度。测量第二测量位置的沟槽中的绝缘材料的第二厚度，并且监测基于第一厚度和第二厚度的值作为用于集成电路结构的抛光工艺参数。

9. 发明授权

US07824946B1 Isolated metal plug process for use in fabricating carbon nanotube memory cells 有权
标题翻译：用于制造碳纳米管记忆单元的隔离金属塞工艺
公开(公告)号：US07824946B1
公开(公告)日：2010-11-02
申请号：US11429069
申请日：2006-05-05
申请人： Richard J. Carter , Peter A. Burke , Verne C. Hornback , Claude L. Bertin , Thomas Rueckes
发明人： Richard J. Carter , Peter A. Burke , Verne C. Hornback , Claude L. Bertin , Thomas Rueckes
IPC分类号： H01L21/00 , H01L21/64
CPC分类号： H01H1/0094 , Y10S977/724 , Y10S977/732 , Y10S977/943
摘要： The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor.
摘要翻译：本发明涉及制造具有纳米管横杆元件的机电存储器单元的结构和方法。这种存储单元包括具有与晶体管电接触的接触的晶体管的衬底。第一支撑层形成在衬底上，其开口限定了电触点上方的下腔室。纳米管横杆元件布置成跨越下室。第二支撑层形成有开口，所述开口限定在所述下腔室上方的顶部腔室，所述顶部腔室包括延伸超出所述下部腔室的边缘以暴露所述第一支撑层的顶部表面的一部分的延伸区域。屋顶层覆盖顶部室的顶部，并且包括露出顶部室的延伸区域的一部分并且包括延伸到顶部层中的孔中以密封顶部和底部室的插塞的孔。存储单元还包括覆盖在横杆元件上的电极，使得电信号可以激活电极以吸引或排斥交叉开关元件以设置晶体管的存储状态。

10. 发明授权

US07666701B1 Isolated metal plug process for use in fabricating carbon nanotube memory cells 有权
公开(公告)号：US07666701B1
公开(公告)日：2010-02-23
申请号：US11429069
申请日：2006-05-05
申请人： Richard J. Carter , Peter A. Burke , Verne C. Hornback
发明人： Richard J. Carter , Peter A. Burke , Verne C. Hornback
IPC分类号： H01L21/00 , H01L21/64
摘要： The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor.

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