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1. 发明授权

US08489792B2 Transaction performance monitoring in a processor bus bridge 失效
标题翻译：处理器总线桥中的事务性能监控
公开(公告)号：US08489792B2
公开(公告)日：2013-07-16
申请号：US12979665
申请日：2010-12-28
申请人： Richard J. Byrne , David S. Masters , Steven J. Pollock , Michael R. Betker
发明人： Richard J. Byrne , David S. Masters , Steven J. Pollock , Michael R. Betker
IPC分类号： G06F13/36
CPC分类号： G06F13/4027 , G06F13/4059
摘要： Described embodiments provide a system having a bridge for connecting two different processor buses. A process monitor within the bridge allows for measuring latency of commands issued on a first bus, passing through the bridge, and executed by clients coupled to the second bus. By using identification fields associated with the command, measuring the latency of each command begins with matching the identification field of the command to an integer. As the bridge passes acknowledgements back to the first bus, the monitoring of the command is stopped when an identification field associated with an acknowledgement matches the identification field of the command being monitored. Data collected include the minimum, maximum, total latency, and the number of commands monitored. From this data, the average latency can be easily calculated.
摘要翻译：所描述的实施例提供了一种具有用于连接两个不同处理器总线的桥的系统。桥内的过程监视器允许测量在第一总线上发出的命令的等待时间，通过桥接器并由与第二总线耦合的客户端执行。通过使用与该命令相关联的标识字段，测量每个命令的等待时间是将命令的标识字段与整数进行匹配开始。当桥接器将确认传递回第一总线时，当与确认相关联的识别字段与正在监视的命令的标识字段匹配时，停止对命令的监视。收集的数据包括最小值，最大值，总延迟以及受监视命令数。从这些数据可以很容易地计算平均潜伏期。

2. 发明申请

US20110225337A1 TRANSACTION PERFORMANCE MONITORING IN A PROCESSOR BUS BRIDGE 失效
标题翻译：处理车总线中的交易性能监控
公开(公告)号：US20110225337A1
公开(公告)日：2011-09-15
申请号：US12979665
申请日：2010-12-28
申请人： Richard J. Byrne , David S. Masters , Steven J. Pollock , Michael R. Betker
发明人： Richard J. Byrne , David S. Masters , Steven J. Pollock , Michael R. Betker
IPC分类号： G06F13/36
CPC分类号： G06F13/4027 , G06F13/4059
摘要： Described embodiments provide a system having a bridge for connecting two different processor buses. A process monitor within the bridge allows for measuring latency of commands issued on a first bus, passing through the bridge, and executed by clients coupled to the second bus. By using identification fields associated with the command, measuring the latency of each command begins with matching the identification field of the command to an integer. As the bridge passes acknowledgements back to the first bus, the monitoring of the command is stopped when an identification field associated with an acknowledgement matches the identification field of the command being monitored. Data collected include the minimum, maximum, total latency, and the number of commands monitored. From this data, the average latency can be easily calculated.
摘要翻译：所描述的实施例提供了一种具有用于连接两个不同处理器总线的桥的系统。桥内的过程监视器允许测量在第一总线上发出的命令的等待时间，通过桥接器并由与第二总线耦合的客户端执行。通过使用与该命令相关联的标识字段，测量每个命令的等待时间是将命令的标识字段与整数进行匹配开始。当桥接器将确认传递回第一总线时，当与确认相关联的识别字段与正在监视的命令的标识字段匹配时，停止对命令的监视。收集的数据包括最小值，最大值，总延迟以及受监视命令数。从这些数据可以很容易地计算平均潜伏期。

3. 发明授权

US08489794B2 Processor bus bridge for network processors or the like 失效
标题翻译：用于网络处理器的处理器总线桥等
公开(公告)号：US08489794B2
公开(公告)日：2013-07-16
申请号：US12979800
申请日：2010-12-28
申请人： Richard J. Byrne , Michael R. Betker
发明人： Richard J. Byrne , Michael R. Betker
IPC分类号： G06F13/36
CPC分类号： G06F13/4027 , G06F13/4059
摘要： Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a command from a first bus, the command having an identification field having a value. The command is then entered into a buffer in the bridge unless another command having the same identification field value exists in the buffer. Once the command with the same identification field value is removed from the buffer, the received command is entered into the buffer. Next, the buffered command is transmitted over a second bus. A response to the command is eventually received from the second bus, the response is transmitted over the first bus, and the command is then removed from the buffer. By not entering the received command until a similar command with the same identification value is removed from the buffer, command ordering is enforced even though multiple commands are pending in the buffer.
摘要翻译：所描述的实施例提供了一种具有用于连接两个不同处理器总线的桥的系统。桥接器从第一总线接收命令，该命令具有具有值的识别字段。然后，该命令被输入到桥中的缓冲器中，除非在缓冲器中存在具有相同标识字段值的另一命令。一旦从缓冲区中删除具有相同标识字段值的命令，则将接收到的命令输入缓冲区。接下来，缓冲命令通过第二总线传输。最终从第二总线接收对该命令的响应，通过第一总线发送响应，然后从缓冲器中移除命令。直到从缓冲区中删除具有相同标识值的类似命令，才能输入接收到的命令，即使缓冲区中有多个命令正在等待，也会执行命令排序。

4. 发明申请

US20110225334A1 PROCESSOR BUS BRIDGE FOR NETWORK PROCESSORS OR THE LIKE 失效
标题翻译：网络处理器的处理器总线或类似的
公开(公告)号：US20110225334A1
公开(公告)日：2011-09-15
申请号：US12979800
申请日：2010-12-28
申请人： Richard J. Byrne , Michael R. Betker
发明人： Richard J. Byrne , Michael R. Betker
IPC分类号： G06F13/42
CPC分类号： G06F13/4027 , G06F13/4059
摘要： Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a command from a first bus, the command having an identification field having a value. The command is then entered into a buffer in the bridge unless another command having the same identification field value exists in the buffer. Once the command with the same identification field value is removed from the buffer, the received command is entered into the buffer. Next, the buffered command is transmitted over a second bus. A response to the command is eventually received from the second bus, the response is transmitted over the first bus, and the command is then removed from the buffer. By not entering the received command until a similar command with the same identification value is removed from the buffer, command ordering is enforced even though multiple commands are pending in the buffer.
摘要翻译：所描述的实施例提供了一种具有用于连接两个不同处理器总线的桥的系统。桥接器从第一总线接收命令，该命令具有具有值的识别字段。然后，该命令被输入到桥中的缓冲器中，除非在缓冲器中存在具有相同标识字段值的另一命令。一旦从缓冲区中删除具有相同标识字段值的命令，则将接收到的命令输入缓冲区。接下来，缓冲命令通过第二总线传输。最终从第二总线接收对该命令的响应，通过第一总线发送响应，然后从缓冲器中移除命令。直到从缓冲区中删除具有相同标识值的类似命令，才能输入接收到的命令，即使缓冲区中有多个命令正在等待，也会执行命令排序。

5. 发明授权

US4757422A Dynamically balanced ionization blower 失效
标题翻译：动平衡电离鼓风机
公开(公告)号：US4757422A
公开(公告)日：1988-07-12
申请号：US906907
申请日：1986-09-15
申请人： Peter R. Bossard , Robert H. Dunphy, Jr. , Michael R. Betker
发明人： Peter R. Bossard , Robert H. Dunphy, Jr. , Michael R. Betker
IPC分类号： H01T23/00 , H05F3/04
CPC分类号： H01T23/00
摘要： A dynamically balanced ion generator is provided which incorporates a detection screen and feedback loop to ensure that the number of positive and negative ions emitted from the generator are substantially equal. The detection screen is located between the ion generating electrodes and the exit port of the device, and is contructed of conductive material which captures a predetermined percentage of ions emitted by the electrodes. The detected imbalance is corrected through a feedback loop comprising an operational amplifier circuit, a low pass filter, a balance control comparator, variable duty cycle oscillator. By varying the duty cycle of the variable duty cycle oscillator, the voltage applied to the primary of a high voltage transformer is controlled such that the relative concentrations of positive and negative ions generated may be altered to compensate for any detected imbalance.
摘要翻译：提供了一种动态平衡的离子发生器，其包括检测屏和反馈环，以确保从发生器发射的正离子和负离子的数量基本相等。检测屏位于离子发生电极和器件的出口之间，并且被构成为捕获由电极发射的预定百分比的离子的导电材料。检测到的不平衡通过包括运算放大器电路，低通滤波器，平衡控制比较器，可变占空比振荡器的反馈回路来校正。通过改变可变占空比振荡器的占空比，控制施加到高压变压器的初级的电压，使得可以改变所产生的正和负离子的相对浓度以补偿任何检测到的不平衡。

6. 发明申请

US20110225391A1 HASH PROCESSING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE 有权
标题翻译：网络通信处理器架构中的HASH处理
公开(公告)号：US20110225391A1
公开(公告)日：2011-09-15
申请号：US13046717
申请日：2011-03-12
申请人： William Burroughs , Deepak Mital , Mohammed Reza Hakami , Michael R. Betker
发明人： William Burroughs , Deepak Mital , Mohammed Reza Hakami , Michael R. Betker
IPC分类号： G06F12/08
CPC分类号： G06F15/167 , G06F9/3851 , G06F9/3885 , H04L45/7453
摘要： Described embodiments provide a hash processor for a system having multiple processing modules and a shared memory. The hash processor includes a descriptor table with N entries, each entry corresponding to a hash table of the hash processor. A direct mapped table in the shared memory includes at least one memory block including N hash buckets. The direct mapped table includes a predetermined number of hash buckets for each hash table. Each hash bucket includes one or more hash key and value pairs, and a link value. Memory blocks in the shared memory include dynamic hash buckets available for allocation to a hash table. A dynamic hash bucket is allocated to a hash table when the hash buckets in the direct mapped table are filled beyond a threshold. The link value in the hash bucket is set to the address of the dynamic hash bucket allocated to the hash table.
摘要翻译：描述的实施例为具有多个处理模块和共享存储器的系统提供散列处理器。散列处理器包括具有N个条目的描述符表，每个条目对应于散列处理器的散列表。共享存储器中的直接映射表包括至少一个包括N个散列桶的存储器块。直接映射表包括用于每个散列表的预定数量的散列桶。每个哈希桶包括一个或多个哈希键和值对以及链接值。共享内存中的内存块包括可用于分配到散列表的动态哈希桶。当直接映射表中的哈希桶被填充超过阈值时，动态哈希桶被分配给散列表。哈希桶中的链路值被设置为分配给哈希表的动态哈希桶的地址。

7. 发明授权

US08539199B2 Hash processing in a network communications processor architecture 有权
标题翻译：网络通讯处理器架构中的哈希处理
公开(公告)号：US08539199B2
公开(公告)日：2013-09-17
申请号：US13046717
申请日：2011-03-12
申请人： William Burroughs , Deepak Mital , Mohammed Reza Hakami , Michael R. Betker
发明人： William Burroughs , Deepak Mital , Mohammed Reza Hakami , Michael R. Betker
IPC分类号： G06F12/08
CPC分类号： G06F15/167 , G06F9/3851 , G06F9/3885 , H04L45/7453
摘要： Described embodiments provide a hash processor for a system having multiple processing modules and a shared memory. The hash processor includes a descriptor table with N entries, each entry corresponding to a hash table of the hash processor. A direct mapped table in the shared memory includes at least one memory block including N hash buckets. The direct mapped table includes a predetermined number of hash buckets for each hash table. Each hash bucket includes one or more hash key and value pairs, and a link value. Memory blocks in the shared memory include dynamic hash buckets available for allocation to a hash table. A dynamic hash bucket is allocated to a hash table when the hash buckets in the direct mapped table are filled beyond a threshold. The link value in the hash bucket is set to the address of the dynamic hash bucket allocated to the hash table.
摘要翻译：描述的实施例为具有多个处理模块和共享存储器的系统提供散列处理器。散列处理器包括具有N个条目的描述符表，每个条目对应于散列处理器的散列表。共享存储器中的直接映射表包括至少一个包括N个散列桶的存储器块。直接映射表包括用于每个散列表的预定数量的散列桶。每个哈希桶包括一个或多个哈希键和值对以及链接值。共享内存中的内存块包括可用于分配到散列表的动态哈希桶。当直接映射表中的哈希桶被填充超过阈值时，动态哈希桶被分配给散列表。哈希桶中的链路值被设置为分配给哈希表的动态哈希桶的地址。

8. 发明授权

US08255644B2 Network communications processor architecture with memory load balancing 失效
标题翻译：具有内存负载平衡的网络通信处理器架构
公开(公告)号：US08255644B2
公开(公告)日：2012-08-28
申请号：US12782393
申请日：2010-05-18
申请人： David P. Sonnier , Michael R. Betker
发明人： David P. Sonnier , Michael R. Betker
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F15/167 , H04L49/101 , H04L49/109 , H04L49/506
摘要： Described embodiments provide a memory system including a plurality of addressable memory arrays. Data in the arrays is accessed by receiving a logical address of data in the addressable memory array and computing a hash value based on at least a part of the logical address. One of the addressable memory arrays is selected based on the hash value. Data in the selected addressable memory array is accessed using a physical address based on at least part of the logical address not used to compute the hash value. The hash value is generated by a hash function to provide essentially random selection of each of the addressable memory arrays.
摘要翻译：所描述的实施例提供了包括多个可寻址存储器阵列的存储器系统。通过接收可寻址存储器阵列中的数据的逻辑地址并基于逻辑地址的至少一部分来计算散列值来访问阵列中的数据。基于哈希值来选择可寻址存储器阵列之一。基于不用于计算哈希值的逻辑地址的至少一部分，使用物理地址访问所选择的可寻址存储器阵列中的数据。哈希值由哈希函数生成，以提供每个可寻址存储器阵列的基本随机选择。

9. 发明申请

US20100293345A1 NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE WITH MEMORY LOAD BALANCING 失效
标题翻译：网络通信处理器架构与内存负载均衡
公开(公告)号：US20100293345A1
公开(公告)日：2010-11-18
申请号：US12782393
申请日：2010-05-18
申请人： David P. Sonnier , Michael R. Betker
发明人： David P. Sonnier , Michael R. Betker
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F15/167 , H04L49/101 , H04L49/109 , H04L49/506
摘要： Described embodiments provide a memory system including a plurality of addressable memory arrays. Data in the arrays is accessed by receiving a logical address of data in the addressable memory array and computing a hash value based on at least a part of the logical address. One of the addressable memory arrays is selected based on the hash value. Data in the selected addressable memory array is accessed using a physical address based on at least part of the logical address not used to compute the hash value. The hash value is generated by a hash function to provide essentially random selection of each of the addressable memory arrays.
摘要翻译：所描述的实施例提供了包括多个可寻址存储器阵列的存储器系统。通过接收可寻址存储器阵列中的数据的逻辑地址并基于逻辑地址的至少一部分来计算散列值来访问阵列中的数据。基于哈希值来选择可寻址存储器阵列之一。基于不用于计算哈希值的逻辑地址的至少一部分，使用物理地址访问所选择的可寻址存储器阵列中的数据。哈希值由哈希函数生成，以提供每个可寻址存储器阵列的基本随机选择。

10. 发明授权

US6052766A Pointer register indirectly addressing a second register in the processor core of a digital processor 有权
标题翻译：指针寄存器间接寻址数字处理器的处理器内核中的第二个寄存器
公开(公告)号：US6052766A
公开(公告)日：2000-04-18
申请号：US135605
申请日：1998-08-18
申请人： Michael R. Betker , John S. Fernando , Frank Lemmon , Shaun P. Whalen
发明人： Michael R. Betker , John S. Fernando , Frank Lemmon , Shaun P. Whalen
IPC分类号： G06F9/30 , G06F12/00
CPC分类号： G06F9/30098
摘要： A first register stores a value that can be used as a pointer to indirectly address a second register. The first register is referred to as a pointer register and the pointer as a register pointer. The second register may be a conventional register that stores a conventional register value (i.e., a data value or a pointer to a data value stored in external memory) or another pointer register. In certain embodiments, a pointer register can also be used to store conventional register values. Pointer registers of the present invention can be used to implement efficiently certain types of digital processing, such as circular buffers, vector processing, convolutional processing, and partitioned processing, using data in registers rather than memory.
摘要翻译：第一个寄存器存储可用作间接寻址第二寄存器的指针的值。第一个寄存器称为指针寄存器，指针作为寄存器指针。第二寄存器可以是常规寄存器，其存储常规寄存器值（即，数据值或指向存储在外部存储器中的数据值的指针）或另一个指针寄存器。在某些实施例中，指针寄存器也可用于存储常规寄存器值。可以使用本发明的指针寄存器来使用寄存器而不是存储器中的数据来有效地实现某些类型的数字处理，例如循环缓冲器，向量处理，卷积处理和分区处理。

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