专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08238362B2 Burst processing modem and related methods 有权
标题翻译：突发处理调制解调器及相关方法
公开(公告)号：US08238362B2
公开(公告)日：2012-08-07
申请号：US12641096
申请日：2009-12-17
申请人： Richard Hollingsworth Cannon , John Scott Crockett , Cris M. Mamaril , Mark Dale
发明人： Richard Hollingsworth Cannon , John Scott Crockett , Cris M. Mamaril , Mark Dale
IPC分类号： H04J3/00 , H04B1/38
CPC分类号： H04L1/0071 , H04L1/0045
摘要： A burst processing modem and related methods. Implementations of a first method of demodulating bursts from a plurality of channels may include receiving a plurality of channels from a received beam and separating the plurality of channels and storing a plurality of frames in a random access memory (RAM) array with a channelizer where each frame of the plurality of frames includes one or more bursts. The method may include serially reading, using a demodulator in response to receiving a timing signal, a desired burst from a frame stored in the RAM array wherein a burst time plan identifying the desired burst is used by a receive frame state machine to generate the timing signal. The method may include demodulating and decoding the desired burst using a demodulator and a decoder to produce a quantity of packet data, and sending the quantity of packet data to a specified destination.
摘要翻译：突发处理调制解调器及相关方法。解调来自多个信道的突发的第一种方法的实现可以包括从接收的波束接收多个信道，并且分离多个信道并且在随机存取存储器（RAM）阵列中存储多个帧，其中每个信道多个帧的帧包括一个或多个突发。该方法可以包括串行读取，响应于接收定时信号使用解调器从存储在RAM阵列中的帧中的期望脉冲串，其中标识期望脉冲串的突发时间计划由接收帧状态机使用以产生定时信号。该方法可以包括使用解调器和解码器解调和解码期望的突发，以产生一定数量的分组数据，并将分组数据的数量发送到指定的目的地。

2. 发明申请

US20100091825A1 BURST PROCESSING MODEM 有权
标题翻译： BURST处理调制解调器
公开(公告)号：US20100091825A1
公开(公告)日：2010-04-15
申请号：US12640887
申请日：2009-12-17
申请人： Richard Hollingsworth Cannon , John Scott Crockett , Cris M. Mamaril , Mark Dale
发明人： Richard Hollingsworth Cannon , John Scott Crockett , Cris M. Mamaril , Mark Dale
IPC分类号： H04L5/16
CPC分类号： H04L1/0071 , H04L1/0045
摘要： A burst processing modem. Implementations may include a receive side including a channelizer adapted to process a plurality of channels and write a plurality of frames to a receive RAM array. A receive frame state machine may be adapted to generate a timing signal using a burst time plan for the plurality of frames. A demodulator may be coupled with the receive RAM array and adapted to read from the receive RAM array only the one or more bursts from the plurality of frames indicated by the timing signal. A transmit side may include a modulator coupled with a transmit frame state machine, with a transmit RAM array, and a combiner bank. The combiner bank may read the modulated plurality of channels from the transmit RAM array and assemble a plurality of frames using a timing signal generated from a burst time plan by the transmit frame state machine.
摘要翻译：突发处理调制解调器实现可以包括接收侧，包括适于处理多个信道并且将多个帧写入接收RAM阵列的信道化器。接收帧状态机可以适于使用针对所述多个帧的突发时间计划来生成定时信号。解调器可以与接收RAM阵列耦合，并且适于仅从接收RAM阵列读取来自由定时信号指示的多个帧中的一个或多个突发。发送侧可以包括与发送帧状态机耦合的调制器，发送RAM阵列和组合器组。组合器组可以从发送RAM阵列读取经调制的多个信道，并使用由发送帧状态机从突发时间计划生成的定时信号来组合多个帧。

3. 发明申请

US20120128047A1 BURST PROCESSING MODEM 有权
标题翻译： BURST处理调制解调器
公开(公告)号：US20120128047A1
公开(公告)日：2012-05-24
申请号：US13363254
申请日：2012-01-31
申请人： Richard Hollingsworth Cannon , John Scott Crockett , Cris M. Mamaril , Mark Dale
发明人： Richard Hollingsworth Cannon , John Scott Crockett , Cris M. Mamaril , Mark Dale
IPC分类号： H04B1/38
CPC分类号： H04L1/0071 , H04L1/0045
摘要： A burst processing modem. Implementations may include a receive side including a channelizer adapted to process a plurality of channels and write a plurality of frames to a receive RAM array. A receive frame state machine may be adapted to generate a timing signal using a burst time plan for the plurality of frames. A demodulator may be coupled with the receive RAM array and adapted to read from the receive RAM array only the one or more bursts from the plurality of frames indicated by the timing signal. A transmit side may include a modulator coupled with a transmit frame state machine, with a transmit RAM array, and a combiner bank. The combiner bank may read the modulated plurality of channels from the transmit RAM array and assemble a plurality of frames using a timing signal generated from a burst time plan by the transmit frame state machine.
摘要翻译：突发处理调制解调器实现可以包括接收侧，包括适于处理多个信道并且将多个帧写入接收RAM阵列的信道化器。接收帧状态机可以适于使用针对所述多个帧的突发时间计划来生成定时信号。解调器可以与接收RAM阵列耦合，并且适于仅从接收RAM阵列读取来自由定时信号指示的多个帧中的一个或多个突发。发送侧可以包括与发送帧状态机耦合的调制器，发送RAM阵列和组合器组。组合器组可以从发送RAM阵列读取经调制的多个信道，并使用由发送帧状态机从突发时间计划生成的定时信号来组合多个帧。

4. 发明授权

US08107515B2 Burst processing modem 有权
标题翻译：突发处理调制解调器
公开(公告)号：US08107515B2
公开(公告)日：2012-01-31
申请号：US12640887
申请日：2009-12-17
申请人： Richard Hollingsworth Cannon , John Scott Crockett , Cris M. Mamaril , Mark Dale
发明人： Richard Hollingsworth Cannon , John Scott Crockett , Cris M. Mamaril , Mark Dale
IPC分类号： H04B1/38 , H04L5/16
CPC分类号： H04L1/0071 , H04L1/0045
摘要： A burst processing modem. Implementations may include a receive side including a channelizer adapted to process a plurality of channels and write a plurality of frames to a receive RAM array. A receive frame state machine may be adapted to generate a timing signal using a burst time plan for the plurality of frames. A demodulator may be coupled with the receive RAM array and adapted to read from the receive RAM array only the one or more bursts from the plurality of frames indicated by the timing signal. A transmit side may include a modulator coupled with a transmit frame state machine, with a transmit RAM array, and a combiner bank. The combiner bank may read the modulated plurality of channels from the transmit RAM array and assemble a plurality of frames using a timing signal generated from a burst time plan by the transmit frame state machine.
摘要翻译：突发处理调制解调器实现可以包括接收侧，包括适于处理多个信道并且将多个帧写入接收RAM阵列的信道化器。接收帧状态机可以适于使用针对所述多个帧的突发时间计划来生成定时信号。解调器可以与接收RAM阵列耦合，并且适于仅从接收RAM阵列读取来自由定时信号指示的多个帧中的一个或多个突发。发送侧可以包括与发送帧状态机耦合的调制器，发送RAM阵列和组合器组。组合器组可以从发送RAM阵列读取经调制的多个信道，并使用由发送帧状态机从突发时间计划生成的定时信号来组合多个帧。

5. 发明授权

US08811460B2 Burst processing modem 有权
标题翻译：突发处理调制解调器
公开(公告)号：US08811460B2
公开(公告)日：2014-08-19
申请号：US13363254
申请日：2012-01-31
申请人： Richard Hollingsworth Cannon , John Scott Crockett , Cris M. Mamaril , Mark Dale
发明人： Richard Hollingsworth Cannon , John Scott Crockett , Cris M. Mamaril , Mark Dale
IPC分类号： H04B1/38 , H04L5/16 , H04L1/00
CPC分类号： H04L1/0071 , H04L1/0045
摘要： A burst processing modem. Implementations may include a receive side including a channelizer adapted to process a plurality of channels and write a plurality of frames to a receive RAM array. A receive frame state machine may be adapted to generate a timing signal using a burst time plan for the plurality of frames. A demodulator may be coupled with the receive RAM array and adapted to read from the receive RAM array only the one or more bursts from the plurality of frames indicated by the timing signal. A transmit side may include a modulator coupled with a transmit frame state machine, with a transmit RAM array, and a combiner bank. The combiner bank may read the modulated plurality of channels from the transmit RAM array and assemble a plurality of frames using a timing signal generated from a burst time plan by the transmit frame state machine.
摘要翻译：突发处理调制解调器实现可以包括接收侧，包括适于处理多个信道并且将多个帧写入接收RAM阵列的信道化器。接收帧状态机可以适于使用针对所述多个帧的突发时间计划来生成定时信号。解调器可以与接收RAM阵列耦合，并且适于仅从接收RAM阵列读取来自由定时信号指示的多个帧中的一个或多个突发。发送侧可以包括与发送帧状态机耦合的调制器，发送RAM阵列和组合器组。组合器组可以从发送RAM阵列读取经调制的多个信道，并使用由发送帧状态机从突发时间计划生成的定时信号来组合多个帧。

6. 发明申请

US20100091777A1 BURST PROCESSING MODEM AND RELATED METHODS 有权
标题翻译： BURST处理调制解调器及相关方法
公开(公告)号：US20100091777A1
公开(公告)日：2010-04-15
申请号：US12641096
申请日：2009-12-17
申请人： Richard Hollingsworth Cannon , John Scott Crockett , Cris M. Mamaril , Mark Dale
发明人： Richard Hollingsworth Cannon , John Scott Crockett , Cris M. Mamaril , Mark Dale
IPC分类号： H04L12/56 , H04J3/24
CPC分类号： H04L1/0071 , H04L1/0045
摘要： A burst processing modem and related methods. Implementations of a first method of demodulating bursts from a plurality of channels may include receiving a plurality of channels from a received beam and separating the plurality of channels and storing a plurality of frames in a random access memory (RAM) array with a channelizer where each frame of the plurality of frames includes one or more bursts. The method may include serially reading, using a demodulator in response to receiving a timing signal, a desired burst from a frame stored in the RAM array wherein a burst time plan identifying the desired burst is used by a receive frame state machine to generate the timing signal. The method may include demodulating and decoding the desired burst using a demodulator and a decoder to produce a quantity of packet data, and sending the quantity of packet data to a specified destination.
摘要翻译：突发处理调制解调器及相关方法。解调来自多个信道的突发的第一种方法的实现可以包括从接收的波束接收多个信道，并且分离多个信道并且在随机存取存储器（RAM）阵列中存储多个帧，其中每个信道多个帧的帧包括一个或多个突发。该方法可以包括串行读取，响应于接收定时信号使用解调器从存储在RAM阵列中的帧中的期望脉冲串，其中标识期望脉冲串的突发时间计划由接收帧状态机使用以产生定时信号。该方法可以包括使用解调器和解码器解调和解码期望的突发，以产生一定数量的分组数据，并将分组数据的数量发送到指定的目的地。

7. 发明授权

US08548009B2 Frequency combiner system and related methods 有权
标题翻译：频率合成器系统及相关方法
公开(公告)号：US08548009B2
公开(公告)日：2013-10-01
申请号：US12552576
申请日：2009-09-02
申请人： John Scott Crockett
发明人： John Scott Crockett
IPC分类号： H04J1/02 , H04J15/00
CPC分类号： H03D7/00
摘要： A combiner system for frequency combining and related methods. Implementations may include a plurality of combiner stages each including a deinterleaver, at least one filter, a frequency downconverter, and a frequency upconverter all operatively coupled together. Each of the plurality of combiner stages may be adapted to receive a complex interleaved input signal including two or more input signals each including a bandwidth, to output a complex stage output signal including the two or more input signals, and to alternately place the bandwidth of each of the two or more input signals in an upper portion and in a lower portion of an output bandwidth of the complex stage output signal. The upper portion and lower portion of the output bandwidth may be contiguous within the output bandwidth and joined at a center of the output bandwidth.
摘要翻译：用于频率组合的组合器系统和相关方法。实现可以包括多个组合器级，每个组合器级都包括解交织器，至少一个滤波器，频率下变频器和全部可操作地耦合在一起的上变频器。多个组合器级中的每一个可以适于接收包括两个或多个包括带宽的输入信号的复杂交错输入信号，以输出包括两个或多个输入信号的复数级输出信号，并且交替地将复数级输出信号的输出带宽的上部和下部的两个或更多个输入信号中的每一个。输出带宽的上部和下部可以在输出带宽内连续，并连接在输出带宽的中心。

8. 发明申请

US20090323724A1 FREQUENCY COMBINER SYSTEM AND RELATED METHODS 有权
标题翻译：频率组合系统及相关方法
公开(公告)号：US20090323724A1
公开(公告)日：2009-12-31
申请号：US12552576
申请日：2009-09-02
申请人： John Scott Crockett
发明人： John Scott Crockett
IPC分类号： H04J1/02
CPC分类号： H03D7/00
摘要： A combiner system for frequency combining and related methods. Implementations may include a plurality of combiner stages each including a deinterleaver, at least one filter, a frequency downconverter, and a frequency upconverter all operatively coupled together. Each of the plurality of combiner stages may be adapted to receive a complex interleaved input signal including two or more input signals each including a bandwidth, to output a complex stage output signal including the two or more input signals, and to alternately place the bandwidth of each of the two or more input signals in an upper portion and in a lower portion of an output bandwidth of the complex stage output signal. The upper portion and lower portion of the output bandwidth may be contiguous within the output bandwidth and joined at a center of the output bandwidth.
摘要翻译：用于频率组合的组合器系统和相关方法。实现可以包括多个组合器级，每个组合器级都包括解交织器，至少一个滤波器，频率下变频器和全部可操作地耦合在一起的上变频器。多个组合器级中的每一个可以适于接收包括两个或多个包括带宽的输入信号的复杂交错输入信号，以输出包括两个或多个输入信号的复数级输出信号，并且交替地将复数级输出信号的输出带宽的上部和下部的两个或更多个输入信号中的每一个。输出带宽的上部和下部可以在输出带宽内连续，并连接在输出带宽的中心。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式