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1. 发明授权

US07232526B2 Method and apparatus for controlling material removal from semiconductor substrate using induced current endpointing 有权
标题翻译：用于使用感应电流终点来控制从半导体衬底去除材料的方法和装置
公开(公告)号：US07232526B2
公开(公告)日：2007-06-19
申请号：US10868245
申请日：2004-06-15
申请人： Richard H. Livengood , Paul Winer , Gary Woods , Michael DiBattista
发明人： Richard H. Livengood , Paul Winer , Gary Woods , Michael DiBattista
IPC分类号： B44C1/22
CPC分类号： H01L21/67253 , H01L22/12 , H01L22/26
摘要： A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.
摘要翻译：公开了一种在集成电路制造工艺中控制从半导体衬底去除材料的方法和装置。该方法和装置利用光源或带电粒子束（电子或离子束）在半导体衬底中形成的至少一个P-N结中感应电流。在去除材料期间监测感应电流，并且响应于感应电流进行预定的转变而停止或终止该过程。

2. 发明授权

US06780658B2 Method and apparatus for controlling material removal from a semiconductor substrate using induced current endpointing 有权
标题翻译：用于使用感应电流终点来控制从半导体衬底去除材料的方法和装置
公开(公告)号：US06780658B2
公开(公告)日：2004-08-24
申请号：US10455143
申请日：2003-06-05
申请人： Richard H. Livengood , Paul Winer , Gary Woods , Michael DiBattista
发明人： Richard H. Livengood , Paul Winer , Gary Woods , Michael DiBattista
IPC分类号： H01L2166
CPC分类号： H01L21/67253 , H01L22/12 , H01L22/26
摘要： A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.
摘要翻译：公开了一种在集成电路制造工艺中控制从半导体衬底去除材料的方法和装置。该方法和装置利用光源或带电粒子束（电子或离子束）在半导体衬底中形成的至少一个P-N结中感应电流。在去除材料期间监测感应电流，并且响应于感应电流进行预定的转变而停止或终止该过程。

3. 发明授权

US06355494B1 Method and apparatus for controlling material removal from a semiconductor substrate using induced current endpointing 有权
公开(公告)号：US06355494B1
公开(公告)日：2002-03-12
申请号：US09702052
申请日：2000-10-30
申请人： Richard H. Livengood , Paul Winer , Gary Woods , Michael DiBattista
发明人： Richard H. Livengood , Paul Winer , Gary Woods , Michael DiBattista
IPC分类号： H01L2166
CPC分类号： H01L21/67253 , H01L22/12 , H01L22/26
摘要： A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.

4. 发明授权

US06579732B2 Method and apparatus for controlling material removal from a semiconductor substrate using induced current endpointing 有权
公开(公告)号：US06579732B2
公开(公告)日：2003-06-17
申请号：US10027368
申请日：2001-12-20
申请人： Richard H. Livengood , Paul Winer , Gary Woods , Michael DiBattista
发明人： Richard H. Livengood , Paul Winer , Gary Woods , Michael DiBattista
IPC分类号： H01L2166
CPC分类号： H01L21/67253 , H01L22/12 , H01L22/26
摘要： A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.

5. 发明授权

US06825557B2 Localized backside chip cooling with integrated smart valves 有权
标题翻译：集成智能阀门的局部背面芯片冷却
公开(公告)号：US06825557B2
公开(公告)日：2004-11-30
申请号：US10321339
申请日：2002-12-17
申请人： Michael DiBattista , Richard H. Livengood
发明人： Michael DiBattista , Richard H. Livengood
IPC分类号： H01L2334
CPC分类号： H01L23/34 , H01L23/473 , H01L2224/16 , H01L2924/00014 , H01L2924/09701 , H01L2224/0401
摘要： An integrated circuit device is disclosed. The device comprises a die that has functional units on a first surface and a cooling system arranged adjacent a second surface opposite the first surface. The cooling system comprises a least one microchannel to contain a cooling liquid and to allow flow of the cooling liquid and at least one reservoir arranged adjacent to a region of the die. There is at least one valve between the reservoir and the microchannel to allow the cooling liquid to flow into the reservoir wherein flow of the cooling liquid depends upon a temperature of the die region.
摘要翻译：公开了一种集成电路器件。该装置包括在第一表面上具有功能单元的模具和邻近与第一表面相对的第二表面布置的冷却系统。冷却系统包括至少一个微通道以容纳冷却液体，并允许冷却液体流动，并且至少一个储存器邻近模具的区域布置。在储存器和微通道之间存在至少一个阀，以允许冷却液体流入储存器，其中冷却液体的流动取决于管芯区域的温度。

6. 发明授权

US07183122B2 Physical nano-machining with a scanning probe system for integrated circuit modification 失效
标题翻译：物理纳米加工用扫描探针系统进行集成电路修改
公开(公告)号：US07183122B2
公开(公告)日：2007-02-27
申请号：US10848925
申请日：2004-05-19
申请人： Michael DiBattista , Richard H. Livengood , Elizabeth B. Varner , Randall C. White
发明人： Michael DiBattista , Richard H. Livengood , Elizabeth B. Varner , Randall C. White
IPC分类号： H04L21/00
CPC分类号： H01L21/76892 , G01Q80/00 , H01L21/76898 , H01L22/26
摘要： Nano-machining for circuit edits through the front side or backside of an integrated circuit may be performed using a scanning probe system. The system may create access holes with smaller dimensions and facilitate nano-machining endpoint detection in some embodiments.
摘要翻译：可以使用扫描探针系统来进行通过集成电路的前侧或背面进行电路编辑的纳米加工。在一些实施例中，该系统可以创建具有较小尺寸的进入孔并且促进纳米加工端点检测。

7. 发明申请

US20110101991A1 Techniques Employing Light-Emitting Circuits 有权
标题翻译：采用发光电路的技术
公开(公告)号：US20110101991A1
公开(公告)日：2011-05-05
申请号：US12909127
申请日：2010-10-21
申请人： Martin L. Villafana , Michael DiBattista , Gary Woods
发明人： Martin L. Villafana , Michael DiBattista , Gary Woods
IPC分类号： G01R31/02 , H05B37/02
CPC分类号： H05B33/0896 , G01R31/311 , H01L25/18 , H01L2224/16145 , H01L2225/06513
摘要： A light-emitting circuit includes a light-emitting transistor and a voltage supply in communication with the light-emitting transistor to bias the light-emitting transistor in a reasonably bright state. A reasonably bright state is a state in which light emission approaches the greatest for a given drain-source current in the light-emitting transistor. In one aspect, the light-emitting circuit is in communication with a device under test and configured so that the light-emitting transistor emits photons in a manner indicative of an operation of the device under test. The light-emitting circuit may be disposed in a first semiconductor layer, and the device under test may be disposed in a second semiconductor layer. Further, the first semiconductor layer may be included in a first die, and the second semiconductor layer may be included in a second die.
摘要翻译：发光电路包括发光晶体管和与发光晶体管连通的电压源，以将发光晶体管偏置在相当明亮的状态。相当明亮的状态是发光晶体管中给定的漏 - 源电流的发光接近最大的状态。在一个方面，发光电路与被测器件通信，并被配置为使得发光晶体管以指示被测器件的操作的方式发射光子。发光电路可以设置在第一半导体层中，并且被测器件可以设置在第二半导体层中。此外，第一半导体层可以包括在第一管芯中，并且第二半导体层可以包括在第二管芯中。

8. 发明授权

US08451009B2 Techniques employing light-emitting circuits 有权
标题翻译：采用发光电路的技术
公开(公告)号：US08451009B2
公开(公告)日：2013-05-28
申请号：US12909127
申请日：2010-10-21
申请人： Martin L. Villafana , Michael DiBattista , Gary Woods
发明人： Martin L. Villafana , Michael DiBattista , Gary Woods
IPC分类号： G01R31/02
CPC分类号： H05B33/0896 , G01R31/311 , H01L25/18 , H01L2224/16145 , H01L2225/06513
摘要： A light-emitting circuit includes a light-emitting transistor and a voltage supply in communication with the light-emitting transistor to bias the light-emitting transistor in a reasonably bright state. A reasonably bright state is a state in which light emission approaches the greatest for a given drain-source current in the light-emitting transistor. In one aspect, the light-emitting circuit is in communication with a device under test and configured so that the light-emitting transistor emits photons in a manner indicative of an operation of the device under test. The light-emitting circuit may be disposed in a first semiconductor layer, and the device under test may be disposed in a second semiconductor layer. Further, the first semiconductor layer may be included in a first die, and the second semiconductor layer may be included in a second die.
摘要翻译：发光电路包括发光晶体管和与发光晶体管连通的电压源，以将发光晶体管偏置在相当明亮的状态。相当明亮的状态是发光晶体管中给定的漏 - 源电流的发光接近最大的状态。在一个方面，发光电路与被测器件通信，并被配置为使得发光晶体管以指示被测器件的操作的方式发射光子。发光电路可以设置在第一半导体层中，并且被测器件可以设置在第二半导体层中。此外，第一半导体层可以包括在第一管芯中，并且第二半导体层可以包括在第二管芯中。

9. 发明授权

US5731587A Hot stage for scanning probe microscope 失效
标题翻译：扫描探针显微镜的热台
公开(公告)号：US5731587A
公开(公告)日：1998-03-24
申请号：US695799
申请日：1996-08-12
申请人： Michael DiBattista , Sanjay V. Patel , John L. Gland , Johannes W. Schwank
发明人： Michael DiBattista , Sanjay V. Patel , John L. Gland , Johannes W. Schwank
IPC分类号： B81C1/00 , G01Q30/10 , G01Q30/20 , G21K5/08 , H01J37/20
CPC分类号： G01Q30/10 , G21K5/08 , H01J37/20 , H01J2237/2001 , H01J2237/2065 , Y10S977/86 , Y10S977/871
摘要： A hot stage for a scanning probe microscope includes a substrate having a dielectric window region which is stress compensated to be held in mild tension at elevated temperatures. A heating element is supplied to heat a specimen deposited on the dielectric widow region and the scanning probe microscope is used to observe specimen characteristics at the elevated temperatures. The dielectric window region is configured to be thermally isolated from the rest of the hot stage allowing only a minimum amount of heat to be dissipated into the scanning probe microscope. Temperature sensing resistors are included for monitoring the temperature in the dielectric window region. Conductivity cell electrodes can also be included for sensing the conductivity and capacitance of the specimen. Furthermore, additional control and measurement hardware, such as a temperature sensor circuit, evaluation station, the ramp generator circuit, etc. can be included to provide additional system features.
摘要翻译：用于扫描探针显微镜的热阶段包括具有电介质窗口区域的基底，其被应力补偿以在升高的温度下保持温和的张力。供应加热元件以加热沉积在电介质寡妇区域上的试样，并且使用扫描探针显微镜在升高的温度下观察样品特性。电介质窗口区域被配置为与热台的其余部分热隔离，仅允许最少量的热量散发到扫描探针显微镜中。包含温度检测电阻用于监测电介质窗口区域的温度。还可以包括电导池电极，用于感测样品的电导率和电容。此外，可以包括额外的控制和测量硬件，例如温度传感器电路，评估站，斜坡发生器电路等，以提供额外的系统特征。

10. 发明申请

US20100032302A1 METHOD TO DIRECT PATTERN METALS ON A SUBSTRATE 有权
标题翻译：在基板上直接形成图案金属的方法
公开(公告)号：US20100032302A1
公开(公告)日：2010-02-11
申请号：US12210781
申请日：2008-09-15
申请人： THERESA HOLTERMANN , Anthony Graupera , Michael DiBattista
发明人： THERESA HOLTERMANN , Anthony Graupera , Michael DiBattista
IPC分类号： C25D5/02
CPC分类号： H01J37/3056 , H01J37/317 , H01J37/3178 , H01J2237/006 , H01J2237/31713 , H01J2237/31732 , H01J2237/31737 , H01J2237/31744 , H01J2237/31745 , H01J2237/31749 , H01L21/2885 , H01L21/76898 , H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： A microscopic metallic structure is produced by creating or exposing a patterned region of increased conductivity and then forming a conductor on the region using electrodeposition. In some embodiments, a microscopic metallic structure is formed on a substrate, and then the substrate is etched to remove the structure from the substrate. In some embodiments, a focused beam of gallium ion without a deposition precursor gas scans a pattern on a silicon substrate, to produce a conductive pattern on which a copper structure is then formed by electrochemical deposition of one or more metals. The structure can be freed from the substrate by etching, or can used in place. A beam can be used to access an active layer of a transistor, and then a conductor can be electrodeposited to provide a lead for sensing or modifying the transistor operation while it is functioning.
摘要翻译：通过产生或暴露具有增加的导电性的图案化区域，然后使用电沉积在该区域上形成导体来产生微观金属结构。在一些实施例中，在衬底上形成微观金属结构，然后蚀刻衬底以从衬底去除结构。在一些实施例中，没有沉积前体气体的聚焦聚焦的镓离子束扫描硅衬底上的图案，以产生导电图案，然后通过电化学沉积一种或多种金属形成铜结构。该结构可以通过蚀刻从衬底中脱离，或者可以在适当的位置使用。可以使用光束来访问晶体管的有源层，然后可以将导体电沉积以提供用于在其工作时感测或修改晶体管操作的引线。

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