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1. 发明授权

US08957457B2 Method for manufacturing a semiconductor chip stack device 有权
标题翻译：半导体芯片堆叠装置的制造方法
公开(公告)号：US08957457B2
公开(公告)日：2015-02-17
申请号：US13302884
申请日：2011-11-22
申请人： Richard Fournel , Pierre Dautriche
发明人： Richard Fournel , Pierre Dautriche
IPC分类号： H01L27/118 , H01L25/065 , H01L25/00
CPC分类号： H01L25/0657 , H01L25/50 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06593 , H01L2225/06596 , H01L2924/13091 , H01L2924/00
摘要： A method for manufacturing a semiconductor chip stack device is provided. The method includes forming a first connecting element array on a surface of a first semiconductor chip; forming a second connecting element array on a surface of a second semiconductor chip, the second array comprising more connecting elements than the first array and the pitch of the first array being a multiple of the pitch of the second array; applying the first chip against the second chip; and setting up test signals between the first and second chips to determine the matching between the connecting elements of the first array and the connecting elements of the second array.
摘要翻译：提供一种制造半导体芯片堆叠装置的方法。该方法包括在第一半导体芯片的表面上形成第一连接元件阵列; 在第二半导体芯片的表面上形成第二连接元件阵列，所述第二阵列包括比所述第一阵列更多的连接元件，所述第一阵列的间距是所述第二阵列的间距的倍数; 将第一芯片施加到第二芯片上; 以及在第一和第二芯片之间建立测试信号，以确定第一阵列的连接元件与第二阵列的连接元件之间的匹配。

2. 发明申请

US20120126230A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR CHIP STACK DEVICE 有权
标题翻译：制造半导体芯片堆叠器件的方法
公开(公告)号：US20120126230A1
公开(公告)日：2012-05-24
申请号：US13302884
申请日：2011-11-22
申请人： Richard Fournel , Pierre Dautriche
发明人： Richard Fournel , Pierre Dautriche
IPC分类号： H01L25/04 , G01R31/20 , H01L21/66
CPC分类号： H01L25/0657 , H01L25/50 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06593 , H01L2225/06596 , H01L2924/13091 , H01L2924/00
摘要： A method for manufacturing a semiconductor chip stack device is provided. The method includes forming a first connecting element array on a surface of a first semiconductor chip; forming a second connecting element array on a surface of a second semiconductor chip, the second array comprising more connecting elements than the first array and the pitch of the first array being a multiple of the pitch of the second array; applying the first chip against the second chip; and setting up test signals between the first and second chips to determine the matching between the connecting elements of the first array and the connecting elements of the second array.
摘要翻译：提供一种制造半导体芯片堆叠装置的方法。该方法包括在第一半导体芯片的表面上形成第一连接元件阵列; 在第二半导体芯片的表面上形成第二连接元件阵列，所述第二阵列包括比所述第一阵列更多的连接元件，所述第一阵列的间距是所述第二阵列的间距的倍数; 将第一芯片施加到第二芯片上; 以及在第一和第二芯片之间建立测试信号，以确定第一阵列的连接元件与第二阵列的连接元件之间的匹配。

3. 发明申请

US20110237068A1 METHOD FOR FORMING ELECTRIC VIAS 有权
标题翻译：形成电动六角形的方法
公开(公告)号：US20110237068A1
公开(公告)日：2011-09-29
申请号：US13070774
申请日：2011-03-24
申请人： Richard Fournel , Yves Dodo
发明人： Richard Fournel , Yves Dodo
IPC分类号： H01L21/283
CPC分类号： H01L21/76898
摘要： A method for forming through vias connecting the front surface to the rear surface of a semiconductor substrate, including the steps of: forming openings in the substrate, thermally oxidizing walls of the openings, filling the openings with a sacrificial material, forming electronic components in the substrate, etching the sacrificial material, filling the openings with a metal, and etching the rear surface of the substrate all the way to the bottom of the openings.
摘要翻译：一种用于形成连接半导体衬底的前表面到后表面的通孔的方法，包括以下步骤：在衬底中形成开口，热氧化开口的壁，用牺牲材料填充开口，在蚀刻牺牲材料，用金属填充开口，并将衬底的后表面一直蚀刻到开口的底部。

4. 发明授权

US07372728B2 Magnetic random access memory array having bit/word lines for shared write select and read operations 有权
标题翻译：具有用于共享写入选择和读取操作的位/字线的磁性随机存取存储器阵列
公开(公告)号：US07372728B2
公开(公告)日：2008-05-13
申请号：US11738987
申请日：2007-04-23
申请人： Cyrille Dray , Christophe Frey , Jean Lasseuguette , Sébastien Barasinski , Richard Fournel
发明人： Cyrille Dray , Christophe Frey , Jean Lasseuguette , Sébastien Barasinski , Richard Fournel
IPC分类号： G11C11/14
CPC分类号： G11C11/15
摘要： A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row. A second write signal is applied to one bit line to actuate the second selection circuit/transistor for the column corresponding to that one bit line and cause a write current to flow through the second source-drain path of the actuated second selection circuit/transistor and the corresponding write bit line to write data into at least one memory element in that column.
摘要翻译：随机存取存储器阵列包括排列成行和列的随机存取存储器元件。每行的元素具有字线和写数字线，并且每列的元素具有位线和写位线。用于每行的第一选择电路/晶体管具有耦合在写入数字线中的第一源极 - 漏极通路和耦合到字线的栅极端子。用于每列的第二选择电路/晶体管具有在写位线中耦合的第二源 - 漏路径和耦合到位线的栅极端。第一写入信号被施加到一个字线以激活对应于该一条字线的行的第一选择电路/晶体管，并且使得写入电流流过被激活的第一选择电路/晶体管的第一源极 - 漏极路径，并且相应的写数字行将数据写入该行中的某些存储器元素。第二写入信号被施加到一个位线以启动与该一个位线相对应的列的第二选择电路/晶体管，并且使得写入电流流过被致动的第二选择电路/晶体管的第二源极 - 漏极通路，并且相应的写位线将数据写入该列中的至少一个存储器元件。

5. 发明申请

US20060054952A1 One-time programmable memory device 有权
公开(公告)号：US20060054952A1
公开(公告)日：2006-03-16
申请号：US11142661
申请日：2005-06-01
申请人： Jean-Pierre Schoellkopf , Richard Fournel
发明人： Jean-Pierre Schoellkopf , Richard Fournel
IPC分类号： H01L29/76
CPC分类号： G11C17/16 , G11C11/5692 , Y10S257/903
摘要： A one-time programmable, dual-bit memory device comprises one MOS storage transistor having a semiconductor substrate, first and second active regions formed under the surface of the substrate being separated by a part of the substrate forming a channel region, a gate formed on the surface of the said substrate in line with the channel region and whose respective distal ends are aligned with a part of the first active region and with a part of the second active region, respectively, which gate is permanently held at ground potential, and a gate oxide layer running between the gate and the surface of the substrate. The intact or broken down state between the gate and the first active region determines a stored value of a first bit, and the intact or broken down state between the gate and the second active region determines a stored value of a second bit.

6. 发明申请

US20050219912A1 Electrically erasable and programmable, non-volatile semiconductor memory device having a single layer of gate material, and corresponding memory plane 有权
标题翻译：具有单层栅极材料的电可擦除和可编程的非易失性半导体存储器件以及相应的存储器平面
公开(公告)号：US20050219912A1
公开(公告)日：2005-10-06
申请号：US10511712
申请日：2003-01-31
申请人： Philippe Gendrier , Cyrille Dray , Richard Fournel , Sebastien Poirier , Daniel Caspar , Philippe Candelier
发明人： Philippe Gendrier , Cyrille Dray , Richard Fournel , Sebastien Poirier , Daniel Caspar , Philippe Candelier
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.
摘要翻译：半导体存储器件包括具有单层栅极材料并且包括浮栅晶体管和控制栅的电可擦除可编程非易失性存储单元。浮栅晶体管的源极，漏极和沟道区域形成控制栅极。此外，存储单元包括位于栅极材料层的第一部分和与结合有控制栅极的第二有源区电隔离的第一半导体有源区之间的介电区。该介电区随后形成隧道区，用于在电池擦除期间将存储在浮动栅极中的电荷转移到第一活性区。

7. 发明授权

US06754125B2 Method and device for refreshing reference cells 有权
标题翻译：用于刷新参考单元的方法和装置
公开(公告)号：US06754125B2
公开(公告)日：2004-06-22
申请号：US10062271
申请日：2002-02-01
申请人： Richard Fournel , Leïla Sedjai Aitouarab
发明人： Richard Fournel , Leïla Sedjai Aitouarab
IPC分类号： G11C700
CPC分类号： G11C16/3431 , G11C16/3418
摘要： Reference cells are refreshed in a non-volatile memory that includes a plurality of memory cells. A selected reference cell and a non-used memory cell are read simultaneously, and a signal read from the reference cell is compared to a signal read from the non-used memory cell. A refresh signal for refreshing the reference cell is supplied when the signal read therefrom is less than the signal read from the non-used memory cell.
摘要翻译：参考单元在包括多个存储单元的非易失性存储器中刷新。同时读取选择的参考单元和未使用的存储单元，并将从参考单元读取的信号与从未使用的存储单元读取的信号进行比较。当从其读取的信号小于从未使用的存储单元读取的信号时，提供刷新参考单元的刷新信号。

8. 发明授权

US06728135B2 Memory cell of the famos type having several programming logic levels 有权
标题翻译：具有多个编程逻辑电平的famos类型的存储单元
公开(公告)号：US06728135B2
公开(公告)日：2004-04-27
申请号：US10228164
申请日：2002-08-26
申请人： Cyrille Dray , Daniel Caspar , Richard Fournel
发明人： Cyrille Dray , Daniel Caspar , Richard Fournel
IPC分类号： G11C1600
CPC分类号： H01L29/42324 , H01L29/7887
摘要： The FAMOS memory location comprises a single floating gate (GR) overlapping an active surface of a semiconductor substrate according to at least two asymmetrical overlap profiles (PF1, PF2) so as to define at least two electrodes in the active region. Memory location programming means (MC, SW) are capable of selectively applying different predetermined sets of bias voltages to the electrodes so as to confer at least three programming logic levels on the memory location.
摘要翻译： FAMOS存储器位置包括根据至少两个不对称重叠轮廓（PF1，PF2）与半导体衬底的有源表面重叠的单个浮动栅极（GR），以便在有源区域中限定至少两个电极。存储器位置编程装置（MC，SW）能够选择性地向电极施加不同的预定偏置电压组，以便在存储器位置上赋予至少三个编程逻辑电平。

9. 发明授权

US06366505B1 Device for controlling a translator-type high voltage selector switch 有权
标题翻译：用于控制转换器型高压选择开关的装置
公开(公告)号：US06366505B1
公开(公告)日：2002-04-02
申请号：US09628149
申请日：2000-07-28
申请人： Richard Fournel
发明人： Richard Fournel
IPC分类号： G11C700
CPC分类号： H03K17/102 , H03K3/356113
摘要： A control device is provided for controlling a selector switch of a high voltage input having at least one cascode stage with MOS transistors. The control device includes a reference voltage generation circuit and a control circuit. The reference voltage generation circuit generates reference voltages from the high voltage input and provides one or more output voltages for the biasing of the MOS transistors of the cascode stage. The control circuit controls the reference generation circuit on the basis of a binary control signal, so as to either set the bias voltages at the level of the logic supply voltages to enable the switching of the selector switch even at low values of the high voltage input, or to enable the bias voltages to be set by the reference generation circuit.
摘要翻译：提供控制装置，用于控制具有MOS晶体管的具有至少一个共源共栅级的高电压输入的选择器开关。控制装置包括参考电压产生电路和控制电路。参考电压产生电路从高压输入产生参考电压，并提供一个或多个用于共源共栅级的MOS晶体管的偏置的输出电压。控制电路基于二进制控制信号来控制参考生成电路，以便将偏置电压设置在逻辑电源电压的电平，使得即使在高电压输入的低值时也能切换选择器开关或者使得偏置电压能够被参考生成电路设置。

10. 发明授权

US5666077A Method and apparatus for detecting an operating voltage level in an integrated circuit 失效
标题翻译：用于检测集成电路中的工作电压电平的方法和装置
公开(公告)号：US5666077A
公开(公告)日：1997-09-09
申请号：US257086
申请日：1994-06-09
申请人： Richard Fournel , Mathieu Lisart
发明人： Richard Fournel , Mathieu Lisart
IPC分类号： G01R31/28 , G01R19/165 , H01L21/66 , H01L21/822 , H01L27/04 , H01L29/739 , H03K5/22
CPC分类号： G01R19/16552 , H01L29/7391
摘要： A Zener diode is used to simplify a circuit for detecting the level of an operating voltage with respect to a specified range of use. The semiconductor junction of this Zener diode is biased alternately by one voltage or another. Under these conditions, the avalanche voltage of this Zener diode changes. The operating voltage to be monitored is connected to the cathode of this Zener diode. If the monitored operating voltage is higher than the avalanche voltage of this Zener diode, the diode alternately conducts. If the operating voltage is outside this range, this diode is either permanently on or permanently off. The variations that result therefrom are detected to report whether the operating voltage is correct.
摘要翻译：齐纳二极管用于简化用于检测相对于指定使用范围的工作电压电平的电路。该齐纳二极管的半导体结交替地被一个或多个电压偏置。在这些条件下，该齐纳二极管的雪崩电压发生变化。要监控的工作电压连接到该齐纳二极管的阴极。如果监控的工作电压高于该齐纳二极管的雪崩电压，则二极管交替导通。如果工作电压在该范围之外，则该二极管永久地处于或永久关闭。检测由此产生的变化，以报告工作电压是否正确。

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