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1. 发明申请

US20050219912A1 Electrically erasable and programmable, non-volatile semiconductor memory device having a single layer of gate material, and corresponding memory plane 有权
标题翻译：具有单层栅极材料的电可擦除和可编程的非易失性半导体存储器件以及相应的存储器平面
公开(公告)号：US20050219912A1
公开(公告)日：2005-10-06
申请号：US10511712
申请日：2003-01-31
申请人： Philippe Gendrier , Cyrille Dray , Richard Fournel , Sebastien Poirier , Daniel Caspar , Philippe Candelier
发明人： Philippe Gendrier , Cyrille Dray , Richard Fournel , Sebastien Poirier , Daniel Caspar , Philippe Candelier
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.
摘要翻译：半导体存储器件包括具有单层栅极材料并且包括浮栅晶体管和控制栅的电可擦除可编程非易失性存储单元。浮栅晶体管的源极，漏极和沟道区域形成控制栅极。此外，存储单元包括位于栅极材料层的第一部分和与结合有控制栅极的第二有源区电隔离的第一半导体有源区之间的介电区。该介电区随后形成隧道区，用于在电池擦除期间将存储在浮动栅极中的电荷转移到第一活性区。

2. 发明授权

US06728135B2 Memory cell of the famos type having several programming logic levels 有权
标题翻译：具有多个编程逻辑电平的famos类型的存储单元
公开(公告)号：US06728135B2
公开(公告)日：2004-04-27
申请号：US10228164
申请日：2002-08-26
申请人： Cyrille Dray , Daniel Caspar , Richard Fournel
发明人： Cyrille Dray , Daniel Caspar , Richard Fournel
IPC分类号： G11C1600
CPC分类号： H01L29/42324 , H01L29/7887
摘要： The FAMOS memory location comprises a single floating gate (GR) overlapping an active surface of a semiconductor substrate according to at least two asymmetrical overlap profiles (PF1, PF2) so as to define at least two electrodes in the active region. Memory location programming means (MC, SW) are capable of selectively applying different predetermined sets of bias voltages to the electrodes so as to confer at least three programming logic levels on the memory location.
摘要翻译： FAMOS存储器位置包括根据至少两个不对称重叠轮廓（PF1，PF2）与半导体衬底的有源表面重叠的单个浮动栅极（GR），以便在有源区域中限定至少两个电极。存储器位置编程装置（MC，SW）能够选择性地向电极施加不同的预定偏置电压组，以便在存储器位置上赋予至少三个编程逻辑电平。

3. 发明授权

US07333362B2 Electrically erasable and programmable, non-volatile semiconductor memory device having a single layer of gate material, and corresponding memory plane 有权
标题翻译：具有单层栅极材料的电可擦除和可编程的非易失性半导体存储器件以及相应的存储器平面
公开(公告)号：US07333362B2
公开(公告)日：2008-02-19
申请号：US10511712
申请日：2003-01-31
申请人： Philippe Gendrier , Cyrille Dray , Richard Fournel , Sébastien Poirier , Daniel Caspar , Philippe Candelier
发明人： Philippe Gendrier , Cyrille Dray , Richard Fournel , Sébastien Poirier , Daniel Caspar , Philippe Candelier
IPC分类号： G11C16/04
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.
摘要翻译：半导体存储器件包括具有单层栅极材料并且包括浮栅晶体管和控制栅的电可擦除可编程非易失性存储单元。浮栅晶体管的源极，漏极和沟道区域形成控制栅极。此外，存储单元包括位于栅极材料层的第一部分和与结合有控制栅极的第二有源区电隔离的第一半导体有源区之间的介电区。该介电区随后形成隧道区，用于在电池擦除期间将存储在浮动栅极中的电荷转移到第一活性区。

4. 发明授权

US06667909B2 Method of erasing a FAMOS memory cell and a corresponding memory cell 有权
公开(公告)号：US06667909B2
公开(公告)日：2003-12-23
申请号：US10117446
申请日：2002-04-04
申请人： Richard Fournel , Cyrille Dray , Daniel Caspar
发明人： Richard Fournel , Cyrille Dray , Daniel Caspar
IPC分类号： G11C1604
CPC分类号： G11C16/0416 , G11C16/0408
摘要： A FAMOS memory cell is electrically erased. The FAMOS memory cell may be electrically erased by applying to the substrate a voltage having a value at least 4 volts higher than the lower of a voltage applied to the source and a voltage applied to the drain. The voltage applied to the substrate is also less than a predetermined limit above which the memory cell is destroyed.

5. 发明授权

US06977836B2 Memory device that can be irreversibly programmed electrically 有权
标题翻译：可以不可逆地编程的存储器件
公开(公告)号：US06977836B2
公开(公告)日：2005-12-20
申请号：US10449921
申请日：2003-05-30
申请人： Philippe Gendrier , Daniel Caspar
发明人： Philippe Gendrier , Daniel Caspar
IPC分类号： G11C8/02 , G11C17/16 , G11C17/04 , G11C17/14
CPC分类号： G11C17/16
摘要： A non-volatile memory device includes a memory plane formed from a matrix of memory cells, each including an access transistor and a capacitor. The matrix includes first and second groups of cells laid out in a first and second directions. Each first group includes cells whose transistor gates are connected together by a first metallization, whose upper capacitor electrodes are connected together by a second metallization, and whose transistor sources are not connected together. Each second group includes cells whose transistor sources are connected together by a third metallization, whose transistor gates are not connected together, and whose upper capacitor electrodes are not connected together. The device includes control means capable of applying chosen voltages to the first, second, and third metallizations so as to selectively program a single one of the cells by damaging its dielectric without programming the other cells and without damaging the transistors of the cells.
摘要翻译：非易失性存储器件包括由存储器单元矩阵形成的存储器平面，每个存储器单元包括存取晶体管和电容器。该矩阵包括在第一和第二方向布置的第一组和第二组单元。每个第一组包括其晶体管栅极通过第一金属化连接在一起的单元，其上电容器电极通过第二金属化连接在一起，并且其晶体管源不连接在一起。每个第二组包括其晶体管源通过第三金属化连接在一起的单元，其晶体管栅极不连接在一起，并且其上部电容器电极未连接在一起。该装置包括能够将选择的电压施加到第一，第二和第三金属化的控制装置，以便通过损坏其电介质来选择性地编程单个电池，而不对其它电池进行编程而不损坏电池的晶体管。

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